Variable width pulse generator

A method of generating a variable width pulse, comprising:

• generating a first edge of a pulse circuit signal using a pulse circuit having a group of transistors comprising a stack of two N-channel transistors connecting in series between the pulse circuit and ground;
• generating a reset signal in response to the first edge, the reset signal directly accepting a control signal at a logic element and generating a delay from the first edge by a variable amount using a logic element according to the control signal;
• and
• generating a second edge of the pulse circuit signal in response to the reset signal.

A pulse generator, comprising:

• means for generating a first edge of a pulse circuit signal using a pulse circuit having a group of transistors comprising a stack of two N-channel transistors connecting in series between the pulse circuit and ground;
• means for generating a reset signal in response to the first edge, the reset signal directly accepting a control signal at a logic element and generating a delay from the first edge by a variable amount using a logic element according to the control signal;
• and
• means for generating a second edge of the pulse circuit in response to the reset signal.

A pulse generator circuit, comprising:

• a first pulse generator circuit receiving a reference clock as an input and outputting a first pulse in response to a rising edge of the reference clock;
• a second pulse generator circuit coupled to the first pulse generator circuit and receiving as an input the reference clock, the second pulse generator circuit outputting a second pulse in response to a falling edge of the reference clock;
• one of said pulse generator circuits including a variable delay circuit coupled thereto, accepting a control signal and delaying one of the output pulses by a variable amount to generate a pulse clock signal of variable width;
• and
• a first group of transistors generating a first edge of the first output pulse in response to the rising edge of the reference clock signal, wherein said first group of transistors comprises a stack of two N-channel transistors connected in series between the output of the first pulse generator circuit and ground.