Method and apparatus for routing low-skew clock networks

An integrated circuit chip comprising:

• a plurality of first clock distribution sub-networks each including a first clock input for receiving a clock signal;
• at least one first structured clock buffer having a first size based on a first load of said first clock distribution sub-networks, a first input pin, a first output pin and providing said clock signal to said first clock distribution sub-networks, said first clock input of each of said first clock distribution sub-networks being directly connected to said first output pin of said first structured clock buffer at generally equally spaced intervals along said first output pin measured from each other and from ends of said first output pin;
• a plurality of second clock distribution sub-networks each including a second clock input for receiving said clock signal;
• at least one second structured clock buffer having a second size based on a second load of said second clock distribution sub-networks, a second output pin, a second input pin, and providing said clock signal to said second clock distribution sub-networks, said second clock input of each of said second clock distribution sub-networks being directly connected to said second output pin of said second structured clock buffer at generally equally spaced intervals along said second output pin measured from each other and from ends of said second output pin;
• and
• at least one third structured clock buffer having a third size, a third output pin, and providing said clock signal to said first structured clock buffer and said second structured clock buffer,
• said first input pin of said first structured clock buffer and said second input pin of said second structured clock buffer being directly connected to said third output pin of said third structured clock buffer at generally equally spaced intervals along said third output pin measured from each other and from ends of said third output pin.

A scaleable structured clock buffer for driving clock distribution sub-networks, said structured clock buffer comprising:

• at least one kernel comprising serially connected buffers and nodes positioned between said buffers,
• said nodes of one kernel of said at least one kernel being coupled to corresponding nodes of other ones of said at least one kernel, and
• a number of said at least one kernel included within said structured clock buffer being based on a load of said clock distribution sub-networks to be driven by said structured clock buffer;
• and
• an output pin for connecting directly to each of said clock distribution sub-networks.

A method of designing a clock distribution network comprising steps of:

• identifying characteristics of structures within a circuit;
• organizing said structures into balanced clock distribution sub-networks;
• grouping said clock distribution sub-networks, to form at least one clock distribution network;
• connecting a structured clock buffer directly to each of said at least one clock distribution network;
• and
• sizing said structured clock buffer based on a load of a corresponding one of said at least one clock distribution network.

A method of designing a clock distribution network comprising steps of:

• identifying latency and capacitance characteristics of structures within a circuit;
• organizing said structures into capacitance balanced clock distribution sub-networks;
• grouping said clock distribution sub-networks, to form at least one clock distribution network;
• connecting a structured clock buffer directly to each of said at least one clock distribution network;
• sizing said structured clock buffer based on a load of a corresponding one of said at least one clock distribution network;
• and
• defining connections between said structured clock buffer and an unmodified power grid.