Reduced error asynchronous clock

Abstract

A cascaded delay asynchronous clock (CDAC) for operating control logic (16) to process an event signal. The clock includes a flip-flop (15) for receiving the event signal and generating a clock enable signal and a logic gate (14) connected to the flip-flop (15) for receiving the clock enable signal and generating a clock signal. The clock signal is then communicated to the control logic (16) for use in the control process. The CDAC further includes a plurality of cascaded delays (10) connected in series, such that the first cascaded delay (10) is connected to receive as an input the clock signal, and the last delay (10) is further connected to the logic gate (14). The output of each of the plurality of cascaded delays (10) is fed back to the control logic (16) to generate timing signals. In another aspect of the invention, a variable duty cycle asynchronous clock (VDAC) for operating control logic (40) to process an event signal is disclosed. The clock includes a first flip-flop (32) for receiving the event signal and generating a clock enable signal, decode logic unit (41) adapted to receive the clock enable signal and generate a control signal, and a second flip-flop (34) adapted to receive the control signal and generate a clock signal. The clock signal is communicated to the control logic (40) for use as a timing signal. The VDAC further includes first and second series connected delays (36, 38), wherein the output of each of the delays is fed back to the decode logic unit (41) and control logic (40) to generate timing signals.

Dependencies are inferred from the claim text.