Micropower, minimal area DC sensing power-up reset circuit

In an integrated circuit comprising a DC sensing power-up reset (PUR) circuit, a method for generating a reset signal, the method comprising the steps of:

• (a) receiving a supply voltage at a first terminal of the PUR circuit and a reference voltage corresponding to a low logic state at a second terminal of the PUR circuit;
• (b) coupling the first terminal and a first node with a first transistor when the supply voltage is rising and exceeds a rising trip point voltage;
• (c) coupling the first terminal and the first node with a second transistor when the supply voltage is falling and has not fallen below a falling trip point voltage which is less than the rising trip point voltage;
• (d) limiting, with a resistor coupled between the first node and the second terminal, current flowing through the first and second transistors while the first terminal is coupled to the first node;
• and
• (e) generating a reset signal having a first logic state when the first terminal is coupled to the first node and having a second logic state when the first terminal is not coupled to the first node, wherein the PUR circuit comprises a first inverter coupled at an input terminal to the first node and at an output terminal to a second node, and a second inverter coupled at an input terminal to the second node, wherein the second inverter generates the reset signal at an output terminal, wherein the reset signal is an active low reset signal, wherein the first transistor has a gate terminal coupled to the second terminal.

An integrated circuit comprising a DC sensing power-up reset (PUR) circuit, the PUR circuit comprising:

• (a) a first terminal for receiving a supply voltage and a second terminal for receiving a reference voltage corresponding to a low logic state;
• (b) a first transistor coupled between the first terminal and a first node, wherein the first transistor switches on when the supply voltage is rising and exceeds a rising trip point voltage;
• (c) a second transistor coupled between the first terminal and the first node, wherein the second transistor switches off when the supply voltage falls below a falling trip point voltage which is less than the rising trip point voltage;
• (d) a first inverter coupled at an input terminal to the first node and at an output terminal to a second node, wherein the first inverter is operational while the supply voltage exceeds a logic voltage which is less than the rising trip point voltage, wherein the logic voltage is the minimum voltage needed for the first inverter to be operational;
• and
• (e) a resistor coupled between the first node and the second terminal for pulling the first node down to the reference voltage while the first and second transistors are both off and for limiting current flowing through the first and second transistors while either or both of the first and second transistors is on.

In an integrated circuit comprising a DC sensing power-up reset (PUR) circuit, a method for generating a reset signal, the method comprising the steps of:

• (a) receiving a supply voltage at a first terminal of the PUR circuit and a reference voltage corresponding to a low logic state at a second terminal of the PUR circuit;
• (b) coupling the first terminal and a first node with a first transistor when the supply voltage is rising and exceeds a rising trip point voltage;
• (c) coupling the first terminal and the first node with a second transistor when the supply voltage is falling and has not fallen below a falling trip point voltage which is less than the rising trip point voltage;
• (d) limiting, with a resistor coupled between the first node and the second terminal, current flowing through the first and second transistors while the first terminal is coupled to the first node;
• and
• (e) generating a reset signal having a first logic state when the first terminal is coupled to the first node and having a second logic state when the first terminal is not coupled to the first node, wherein the PUR circuit comprises a first inverter coupled at an input terminal to the first node and at an output terminal to a second node, and a second inverter coupled at an input terminal to the second node, wherein the second inverter generates the reset signal at an output terminal, wherein the reset signal is an active low reset signal, further wherein the first and second inverters are operational while the supply voltage exceeds a logic voltage which is less than the rising trip point voltage, wherein the logic voltage is the minimum voltage needed for the first and second inverters to be operational, wherein the falling trip point voltage is greater than the logic voltage.