Power on reset circuit with power noise immunity

A power on reset circuit for generating a power on reset signal to set logic elements at a desired initialization state during power-up, comprising:

• a first voltage level detector having a first threshold voltage, said first voltage level detector detecting a power supply voltage level to generate a first detection signal as a detection result, the first detection signal having the power supply voltage level when the first threshold voltage is higher than the power supply voltage level;
• a second voltage level detector having a second threshold voltage higher than the first threshold voltage, said second voltage level detector detecting the power supply voltage level to generate a second detection signal as a detection result, the second detection signal having the power supply voltage level when the second threshold voltage is higher than the power supply voltage level;
• and
• a latch circuit generating the power on reset signal in response to the first and second detection signals,
• wherein said latch circuit is set to an initialization state when the power supply voltage level is less than the first threshold voltage during power-up, so that the power on reset signal goes to a logically activated state, and
• wherein said latch circuit is reset when the power supply voltage level is higher than the second threshold voltage, so that the power on reset signal goes to a logically deactivated state.

A power on reset circuit comprising:

• a latch circuit having first and second input terminals and an output terminal that outputs a power on reset signal;
• and
• a latch controller connected to the first and second input terminals and having a first threshold voltage, and a second threshold voltage higher than the first threshold voltage,
• said latch controller setting said latch circuit to an initialization state when a power supply voltage is less than the first threshold voltage during power-up so that the power on reset signal goes to a logically activated state and resetting said latch circuit when the power supply voltage is higher than the second threshold voltage so that the power on reset signal goes to a logically deactivated state,
• said latch circuit comprising
• an inverter having an input terminal that receives the second detection signal and an output terminal,
• a first NOR gate having a first input terminal connected to the output terminal of the inverter, a second input terminal and an output terminal, and
• a second NOR gate having a first input terminal that receives the first detection signal, a second input terminal connected to the output terminal of the first NOR gate, and an output terminal connected to the second input terminal of the first NOR gate.

A method of generating a power-on reset signal comprising:

• generating a first detection signal when a first threshold is greater than a power supply voltage level during power-up, the first detection signal having the power supply voltage level;
• generating a second detection signal when a second threshold is greater than the power supply voltage level, the second detection signal having the power supply voltage level and the second threshold voltage being higher than the first threshold voltage;
• and
• generating the power-on reset signal responsive to the first and second detection signals,
• a voltage difference between the first and second threshold voltages is greater than an oscillation of the power supply voltage level during power-up.

A power on reset circuit comprising:

• a first voltage level detector generating a first detection signal when a first threshold is greater than a power supply voltage level during power-up, the first detection signal having the power supply voltage level;
• a second voltage level detector generating a second detection signal when a second threshold is greater than the power supply voltage level, the second detection signal having the power supply voltage level and the second threshold voltage being higher than the first threshold voltage;
• and
• a latch circuit generating the power-on reset signal responsive to the first and second detection signals,
• a voltage difference between the first and second threshold voltages is greater than an oscillation of the power supply voltage level during power-up.