US 6,204,695 B1Granted

Clock-gating circuit for reducing power consumption

AssigneeXilinx, Inc.

InventorsPeter H. Alfke, Alvin Y. Ching, Scott O. Frake, Jennifer Wong, Steven P. Young

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Abstract

A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

Claims8

Dependent claims

A method of gating a clock signal in a user-defined logic device, the method comprising the steps of:

providing a clock signal to a storage latch of the user-defined logic device, wherein the clock signal transitions between a first logic state and a second logic state;
providing a clock enable signal to the storage latch;
enabling the storage latch to provide a gate control signal representative of the clock enable signal while the clock signal is in the first logic state;
latching the clock enable signal in the storage latch when the clock signal transitions from the first logic state to the second logic state, wherein the clock enable signal remains latched in the storage latch as long as the clock signal remains in the second logic state, the storage latch providing the gate control signal with a value representative of the latched clock enable signal while the clock signal remains in the second logic state;
controlling the gating of the clock signal on the user-defined logic device with the gate control signal;
and
routing the clock signal to an array of configurable logic blocks of the user-defined logic device through a global routing circuit of the user-defined logic device, thereby programmably controlling the configurable logic blocks.

4 more elements

Dependencies are inferred from the claim text.