US 6,204,694 B1 · Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals

Abstract

A circuit and method is described which generates a high frequency clock signal whose frequency is accurate enough to be used for testing other circuitry, yet the circuit can be described using a hardware description language so that it is suitable for logic synthesis and automatic layout. The technique uses a plurality of programmable ring oscillators and means to select and enable one of the ring oscillators. The output frequency is measured relative to that of a lower frequency reference signal, and when the output frequency is incorrect, a different ring oscillator is selected or the present ring oscillator's frequency is changed. Circuitry is included to prevent glitches at the output of the clock generator when the frequency is changed, regardless of how the ring oscillators are constructed. One or more of the delay stages in the ring oscillators contain parallel 3-state logic gates which allow delay changes less than the delay of a single non-inverting delay gate, and this allows the frequency to be very accurately controlled.

Claims28

Dependent claims

A programmable clock signal generation circuit for generating a main clock signal, comprising:

a plurality of programmable ring oscillators, each ring oscillator having multiple delay stages connected in series to form a ring, at least one of the delay stages having programmable delay to produce an internal clock signal with programmable frequency;
an oscillator selector for selecting the internal clock signal of one of ring oscillators to produce the main clock signal;
a comparator for comparing the programmable frequency of the selected internal clock signal with a reference frequency to produce a comparison result;
and
a frequency controller for adjusting the programmable frequency of the selected ring oscillator and controlling the oscillator selector to select the internal clock signal of a different one of the ring oscillators, based on eh comparison result.

2 more elements

A programmable clock signal generation circuit for generating a main clock signal, comprising:

a first oscillator unit having a programmable ring oscillator containing multiple delay stages connected in series to form a ring, at least one of the delay stages having programmable delay to produce an internal clock signal with programmable frequency;
a second oscillator unit having a programmable ring oscillator containing multiple delay stages connected in series to form a ring, at least on of the delay stages having programmable delay to produce an internal clock signal with programmable frequency;
a unit selector for selecting one of the first and second oscillator units as a main oscillator unit to produce the main clock signal from the internal clock signal of the main oscillator unit, and selecting the other one of the first and second oscillator units as a secondary oscillator unit to produce a secondary clock signal from the internal clock signal of the secondary oscillator unit;
a comparator for comparing the programmable frequency of the internal clock signal of the secondary oscillator unit with a reference frequency to produce a comparison result;
a frequency controller for adjusting the programmable frequency of the internal clock signal of the secondary oscillator unit, based on the comparison result;
a unit controller for controlling the unit selector to switch the selection between the main oscillator unit and the secondary oscillator unit when frequency adjustment of the secondary oscillator unit is completed.

3 more elements

A programmable clock signal generation circuit for generating a main clock signal, comprising:

a first oscillator unit having:
a plurality of programmable ring oscillators, each ring oscillator having multiple delay stages connected in series to form a ring, at least one of the delay stages having programmable delay to produce an internal clock signal with programmable frequency;
and
a first oscillator selector for selecting the internal clock signal of one of said ring oscillators of the first oscillator unit;
a second oscillator unit having:
a plurality of programmable ring oscillators, each ring oscillator having multiple delay stages connected in series to form a ring, at least one of the delay stages having programmable delay to produce an internal clock signal with programmable frequency;
and
a second oscillator selector for selector for selecting the internal clock signal of one of said ring oscillators of the second oscillator unit;
a unit selector for selecting one of the firs and second oscillator units as a main oscillator unit to produce the main clock signal from the internal clock signal of the main oscillator unit, and selecting the other one of the first and second oscillator units as a secondary oscillator unit to produce a secondary clock signal form the internal clock signal of the secondary oscillator unit;
a comparator for comparing the programmable frequency of the internal clock signal of a secondary oscillator unit with a reference frequency to produce a comparison result;
a frequency controller for adjusting the programmable frequency of the internal clock signal of the secondary oscillator unit and controlling the first and second oscillator selectors to select a different ring oscillator from the secondary oscillator unit, based on the comparison result;
and
a unit controller for controlling the unit selector to switch the selection between the main oscillator unit and the secondary oscillator unit when frequency adjustment of the secondary oscillator unit is completed.

10 more elements

A programmable clock signal generation circuit for generating a main clock signal, comprising:

a programmable ring oscillator having multiple delay stages connected in series to form a ring, at lest one of the delay stages having programmable delay to produce an oscillator output signal of programmable frequency, the one of the delay stages having:
a delay stage input for receiving a delay stage input signal;
a delay stage output for outputting a delay stage output signal;
a first logic gate connected between the delay stage input and the delay stage output, the first logic gate being enabled during operation of the ring oscillator;
and
a second logic gate connected between the delay stage input and the delay stage output in parallel to the first logic gate, the second logic gate receiving a gate enable signal, the second logic gate being disabled to provide the delay stage output signal with a first impedance and a first frequency when the gate enable signal is inactive, and the second logic gate being enabled to provide the delay stage output signal with a second impedance and a second frequency when the gate enable signal is active, so that the second impedance is smaller than the first impedance, which causes the second frequency to be greater than the first frequency;
a comparator for comparing the programmable frequency of the oscillator output signal with a reference frequency to produce a comparison result;
and
a frequency controller for adjusting the programmable frequency of the oscillator output signal, based on the comparison result.

6 more elements

A method for providing a main clock signal with a target frequency using a programmable clock signal generation circuit having a programmable ring oscillator containing multiple delay stages connected in series to form a ring, at least one of the delay stages having programmable delay to produce an internal clock signal of programmable frequency, the one of the delay stages having:

a delay stage input for receiving a delay stage input signal;
a delay stage output for outputting a delay stage output signal;
a first logic gate connected between the delay stage input and the delay stage output, the first logic gate being enabled during operation of the ring oscillator;
and
a second logic gate connected between the delay stage input and the delay stage output in parallel to the first logic gate, the second logic gate receiving a gate enable signal, the second logic gate being disabled to provide the delay stage output signal with a first impedance and a first frequency when the gate enable signal is inactive, and the second logic gate being enabled to provide the delay stage output signal with a second impedance and a second frqeuncy when the gate enable signal is active, so that the second impedance is smaller than the first impedance, which causes the second frequency to be greater than the first frequency;
the method comprising the steps of:
forcing the logic level of the main clock signal to a predetermined constant value following a predetermined edge in the main clock signal;
adjusting the programmable frequency of a selected ring oscillator;
resetting the selected ring oscillator so that the internal clock signal becomes the same logic level as the main clock signal;
disabling said forcing of the logic level of the main clock signal;
and
re-enabling the selected ring oscillator so that it begins to oscillate and the internal clock signal drives said main clock signal with the target frequency.

9 more elements

A programmable ring oscillator for generating an oscillator output signal with programmable frqeuncy, the ring oscillator comprising multiple delay stages connected in series to form a ring, at lest one of the delay stags having:

a delay stage input for receiving a delay stage input signal;
a delay stage output for outputting a delay stage output signal;
a first logic gate connected between the delay stage input and the delays stage output, the first logic gate being enabled during operation of the ring oscillator;
and
a second logic gate connected between the delay stage input and the delay stage output in parallel to the first logic gate, the second logic gate receiving a gate enable signal, the second logic gate being disabled to provide the delay stage output signal with a first impedance and a first frequency when the gate enable signal is inactive, and the seonc logic gate being enabled to provide the delay stage output signal with a second impedance and a second frequency when the gate enable signal is active, so that the second impedance is smaller than the first impedance, which causes the second frequency to be greater than the first frequency.

2 more elements

A programmable ring oscillator unit for generating a clock signal, the ring oscillator unit comprising:

a plurality of programmable ring oscillators, each ring oscillator having multiple delay stages connected in series to form a ring, at least one of the delay stages having programmable delay to produce an internal clock signal of programmable frequency, the one of the delay stages having:
a delay stage input for receiving a delay stage input signal;
a delay stage output for outputting a delay stage output signal;
a first logic gate connected between the delay stage input and the delay stage output, the first logic gate being enabled during operation of the ring oscillator;
and
a second logic gate connected between the delay stage input and the delay stage output in parallel to the first logic gate, the second logic gate receiving a gate enable signal, the second logic gate being disabled to provide the delay stage output signal with a first impedance and a first frequency when the gate enable signal is inactive, and the second logic gate being enabled to provide the delay stage output signal with a second impedance and a second frequency when the gate enable signal is active, so that the second impedance is smaller than the first impedance, which causes the second frequency to be greater than the first frequency;
and
an oscillator selector for selecting the internal clock signal of one of said ring oscillators to produce the oscillator unit clock signal.

5 more elements

Dependencies are inferred from the claim text.

Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals

Life of this patent

Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals

Life of this patent

Abstract

Claims28