US 6,204,690 B1 · FPGA architecture with offset interconnect lines

Abstract

The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

Claims11

Dependent claims

A programmable logic device, comprising:

a first column of substantially identical tiles, each tile comprising a logic block;
and
a plurality of vertical interconnect lines each spanning a portion of the first column of tiles, each vertical interconnect line having a midpoint physically located substantially at the center of the vertical interconnect line, a top end located substantially at one end of the vertical interconnect line, and a bottom end located substantially at the other end of the vertical interconnect line, the midpoint, top end, and bottom end of the vertical interconnect line all being located in non-adjacent tiles;
wherein in each tile the logic block is programmably coupled to the top end of a first vertical interconnect line, the midpoint of a second vertical interconnect line, and the bottom end of a third vertical interconnect line.

1 more element

A method for designing interconnect lines in an FPGA, comprising:

creating a first column of 2N vertically arranged logic blocks, where N is an integer greater than two;
adding a first interconnect line originating substantially at a 1st logic block at the top of the first column and coupled to the 1st logic block of the first column;
programmably coupling the first interconnect line to an N+1st logic block from the top of the first column;
extending the first interconnect line into a substantially identical lower column located below the first column and programmably coupling the first interconnect line to a 1st logic block in the lower column;
terminating the first interconnect line substantially at the 1st logic block in the lower column;
adding a second interconnect line originating substantially at a 2nd logic block from the top of the first column and coupled to the 2nd logic block of the first column;
programmably coupling the second interconnect line to an N+2nd logic block from the top of the first column;
extending the second interconnect line into the lower column and programmably coupling the second interconnect line to a 2nd logic block in the lower column;
terminating the second interconnect line substantially at the 2nd logic block in the lower column;
and
repeating the adding, programmably coupling, extending, and terminating steps until 2N adjacent logic blocks are each programmably coupled to three interconnect lines.

8 more elements

Dependencies are inferred from the claim text.

FPGA architecture with offset interconnect lines

Life of this patent

FPGA architecture with offset interconnect lines

Life of this patent

Abstract

Claims11