US 6,204,689 B1 · Input/output interconnect circuit for FPGAs

Abstract

An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles. In another embodiment, various ends of bi-directional intermediate-length buses are terminated to long lines through programmable interconnection points (PIPs). In another embodiment, PIPs are provided to enable horizontal long lines to be connected to horizontal intermediate-length buses, which in turn, can be connected to vertical long lines, thereby providing a low-skew, high fanout routing network.

Claims21

Dependent claims

A programmable logic device comprising:

an array of configurable logic elements (CLES) arranged in rows and columns;
a first set of long lines extending along a column of CLEs in a regular pattern;
a first set of intermediate-length buses extending along the column of CLEs in a regular pattern;
a first set of programmable interconnection points (PIPs) for coupling the intermediate length buses to CLEs in the column of CLEs in a regular pattern;
a second set of PIPs for coupling the long lines to the intermediate length buses in a regular pattern;
and
a third set of PIPs located at a first edge of the column of CLEs, wherein the third set of PIPs programmably couples the long lines to the intermediate length buses at the first edge, and wherein the regular pattern of connections between the long lines and the intermediate length buses is maintained by the third set of PIPs.

4 more elements

A programmable logic device comprising:

an array of configurable logic elements (CLEs) arranged in rows and columns;
a first set of long lines extending along a first edge of the array in a regular pattern;
a first set of intermediate-length buses extending along the first edge of the array in a regular pattern;
a first set of programmable interconnection points (PIPs) for coupling the long lines to the intermediate length buses in a regular pattern along the first edge of the array;
and
a second set of PIPs located at a first end of the first edge, wherein the second set of PIPs is configured to terminate the long lines to the intermediate length buses at the first end, the regular pattern of connections between the long lines and the intermediate length buses established by the first set of PIPs being maintained by the second set of PIPs.

3 more elements

Dependencies are inferred from the claim text.

Input/output interconnect circuit for FPGAs

Life of this patent

Input/output interconnect circuit for FPGAs

Life of this patent

Abstract

Claims21