Programmable logic array integrated circuit devices with interleaved logic array blocks

Programmable logic array integrated circuit device circuitry comprising:

• a plurality of programmable logic circuits, each having a plurality of input terminals and an output terminal and being programmable to apply to said output terminal an output signal which is any of a plurality of logic functions of input signals received by said logic circuit via said input terminals;
• a plurality of registers, each of which is associated with a respective one of said programmable logic circuits for selectively registering said output signal of the associated programmable logic circuit, each of said registers having a secondary signal input terminal for receiving a secondary input signal which controls a predetermined aspect of the operation of said register;
• a plurality of interconnection conductors associated with said plurality of programmable logic circuits;
• programmable input signal selection circuitry associated with each of the input terminals of each of the programmable logic circuits for programmably selecting the input signal applied to said input terminal from signals on any of a multiplicity of the interconnection conductors;
• a plurality of signal sources;
• and
• a programmable logic connector for selecting any of said signal sources or said input signal as the source of a first secondary signal which is applied to the secondary signal input terminals of a first subplurality of said programmable logic circuits, and for selecting any of said signal sources or said input signal as the source of a second secondary signal which is applied to the secondary signal input terminals of a second subplurality of said programmable logic circuits.