US 6,204,686 B1Granted

Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources

AssigneeVantis Corporation

InventorsOm P. Agrawal, Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran

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Abstract

A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.

Claims33

Dependent claims

A signal routing method for use in a field programmable gate array (FPGA) device having a plurality of variable grain blocks (VGB's) and differently-directed. interconnect channels interconnecting the VGB's, wherein each VGB includes primitive building blocks that can be programmably folded-together and further wherein each VGB is programmably-configurable to selectively and independently acquire input term signals from adjacent and differently-directed interconnect channels and to produce one or more respective result signals of respective configurable granularities from the acquired signals, and further wherein each VGB is coupled to supply at least one of its result signals to a shared output component (SOC) that is shared by plural VGB's, the SOC having configurable routing means for programmably-routing received result signals to any one or plural ones of the differently-directed ones of the interconnect channels that are adjacent to the SOC,

and further wherein each VGB is programmably-configurable to selectively and independently acquire control signals from its adjacent and differently-directed interconnect channels and to use at least one of its acquired control signals for deriving a respective route-selection signal and supplying the route-selection signal to a corresponding SOC;
said method comprising the steps of:
(a) configuring one or more of said VGB's to each supply as its respective route-selection signal to a corresponding SOC a selection signal that causes the corresponding SOC to route a designated result signal to a pre-identified one or plural ones of the differently-directed, interconnect channels that are adjacent to the SOC;
and
(b) configuring at least one of said VGB's to produce and supply said designated result signal to the corresponding SOC so that said designated result signal will be routed to the pre-identified one or plural ones of the differently-directed, interconnect channels that are adjacent to the corresponding SOC.

2 more elements

A configuring method for configuring a field programmable gate array (FPGA) device to provide for flexible transmission of a first function signal produced by a respectively placed implementation of a first function generator within a corresponding first of plural variable grain blocks (VGB's) disposed as an array in the FPGA device, where the provided flexible transmission allows the first function signal to be transmitted by way of specialized lines within differently-directed, VGB-interconnecting channels to other of the VGB's that are arbitrarily distal from the first VGB by a distance within the reach of the specialized VGB-interconnecting lines and along one or the other of the different directions of the VGB-interconnecting channels, said VGB-interconnecting channels also including general-interconnect resources that can be programmed to alternatively or additionally transmit the first function signal through one or more switchboxes to said other of the VGB's, said transmission through the switchboxes causing a greater signal propagation delay than said corresponding transmission through one or more of the specialized lines;

wherein:
(0.1) each specialized line continuously spans a distance of at least 8 VGB's;
(0.2) each VGB has two differently-directed, VGB-interconnecting channels extending adjacent to that VGB;
(0.3) each VGB includes input term signal acquiring fingers each for independently and selectively acquiring a respective input term signal from an adjacent interconnect channel, the input term signal acquiring fingers of the VGB being able to acquire their input term signals from the differently-directed, VGB-interconnecting channels that extend adjacent to that VGB;
(0.4) each VGB includes programmably-compoundable and independently-configurable, function building blocks that are coupled to the VGB's input term signal acquiring fingers and that can independently produce from the acquired input term signals, respective ones of primitive function signals and can, if compounded-together, produce a corresponding one or more, more complex function signals;
(0.5) each VGB includes a programmably-configurable, post-acquisition decoder circuit interposed between the VGB's input term signal acquiring fingers and the VGB's function building blocks for transparently passing the VGB's acquired input term signals to, or duplicatively rerouting one or more of the VGB's acquired input term signals to, the VGB's function building blocks so as to support respective synthesizings of said primitive function signals and said more complex function signals in the VGB;
(0.6) each VGB includes control signal acquiring fingers each for independently and selectively acquiring a respective control signal from an adjacent interconnect channel, the control signal acquiring fingers of the VGB being able to acquire their control signals from the differently-directed, VGB-interconnecting channels that extend adjacent to that VGB;
(0.7) for each sharing group of at least two VGB's the FPGA device has a corresponding, shared output component (SOC) that is coupled to the sharing group and to the specialized lines in differently-directed, VGB-interconnecting channels that extend adjacent to that SOC, where:
(0.7a) the SOC is configurable to selectively receive respective function signals produced from the SOC's group of sharing VGB's, and
(0.7b) the SOC is configurable to selectively output its received function signals, each to one or both of the specialized lines in differently-directed ones of the VGB-interconnecting channels that extend adjacent to that SOC;
and wherein said FPGA configuring method comprises:
(a) programming at least a first of said VGB's to produce a respective first function signal from input term signals acquired by the first VGB from at least one of the differently-directed, VGB-interconnecting channels that extend adjacent to that first VGB;
and
(b) programming a corresponding first SOC that is shared by the sharing group of the first VGB so that the first SOC outputs the first function signal to at least one of the specialized lines in the differently-directed ones of the VGB-interconnecting channels that extend adjacent to that SOC.

11 more elements

A programmed FPGA device comprising:

(a) a plurality of variable grain blocks (VGB's) disposed as an array in the FPGA device;
(b) a plurality of differently-directed, VGB-interconnecting channels each having specialized lines, each specialized line being for transmitting a given first function signal sourced from a respectively given first VGB adjacent to the specialized line, the transmission being to corresponding others of the VGB's that are arbitrarily distal from the respectively given first VGB by a distance that is within the reach of the specialized VGB-interconnecting line and along one or the other of the different directions of the specialized line's respective VGB-interconnecting channel, said VGB-interconnecting channels also including general-interconnect resources that can be programmed to alternatively or additionally transmit the first function signal from a respectively given VGB and through one or more switchboxes to corresponding others of the VGB's, said transmission through the switchboxes causing a greater signal propagation delay than said corresponding transmission through one or more of the specialized lines;
(b.1) wherein each specialized line continuously spans a distance of at least 8 VGB's;
(b.2) wherein each VGB has two differently-directed, VGB-interconnecting channels extending adjacent to that VGB;
(b.3) wherein each VGB includes input term signal acquiring fingers each for independently and selectively acquiring a respective input term signal from an adjacent interconnect channel, the input term signal acquiring fingers of the VGB being able to acquire their input term signals from the differently-directed, VGB-interconnecting channels that extend adjacent to that VGB;
(b.4) wherein each VGB includes programmably-compoundable and independently-configurable, function building blocks that are coupled to the VGB's input term signal acquiring fingers and that can independently produce from the acquired input term signals, respective ones of primitive function signals and can, if compounded-together, produce a corresponding one or more, more complex function signals;
(b.5) wherein each VGB includes a programmably-configurable, post-acquisition decoder circuit interposed between the VGB's input term signal acquiring fingers and the VGB's function building blocks for transparently passing the VGB's acquired input term signals to, or duplicatively rerouting one or more of the VGB's acquired input term signals to, the VGB's function building blocks so as to support respective synthesizings of said primitive function signals and said more complex function signals in the VGB;
(b.6) wherein for each sharing group of at least two VGB's, the FPGA device has a corresponding, shared output component (SOC) that is coupled to the sharing group and to the specialized lines in differently-directed, VGB-interconnecting channels that extend adjacent to that SOC, where:
(0.6a) the SOC is configurable to selectively receive respective function signals produced from the SOC's group of sharing VGB's, and
(0.6b) the SOC is configurable to selectively output its received function signals, each to one or both of the specialized lines in differently-directed ones of the VGB-interconnecting channels that extend adjacent to that SOC;
and wherein said programmed FPGA device is characterized by:
(c) at least a first one of said VGB's being programmed to produce a respective first function signal from input term signals acquired by the first VGB from at least one of the differently-directed, VGB-interconnecting channels that extend adjacent to that first VGB;
and
(d) a corresponding first SOC that is shared by the sharing group of the first VGB being programmed so that the first SOC outputs the first function signal to at least one of the specialized lines in the differently-directed ones of the VGB-interconnecting channels that extend adjacent to that first SOC.

11 more elements

Dependencies are inferred from the claim text.