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US 6,204,679 B1Granted
Low cost memory tester with high throughput
AssigneeTeradyne, Inc.
InventorWalter Gray, III
Life of this patent
Estimating the term…
Abstract
An automatic test system for testing semiconductor devices, particularly memory devices. The test system includes a handling device with several temperature controlled chambers, each associated with a test head. Trays of devices are loaded into the handling device and are brought to thermal equilibrium in each chamber before being tested. The number of test sites within each chamber is varied in inverse proportion to the time it takes to test a device at the temperature within the chamber.
Claims10
A test system for semiconductor chips having:
- a) a plurality of independently controllable test heads for generating respective sets of test signals;
- b) a handler having a plurality of interconnected temperature chambers corresponding to said plurality of test heads, each of said temperature chambers including
- a set of contactors connected to a corresponding test head and adapted to couple to a stream of semiconductor devices moving through said temperature chamber.
A test system for semiconductor chips having:
- a) a plurality of independently controllable test heads for generating respective sets of test signals;
- b) a handler having a plurality of interconnected temperature chambers corresponding to said plurality of test heads, each of said temperature chambers including
- a set of contactors connected to a corresponding test head and adapted to couple to a stream of semiconductor chips moving through said temperature chamber;
- and
- c) a tester mainframe comprising
- a plurality of independently controlled pattern generators, each generator being connected to one of said test heads, and
- support circuitry connected to all of said plurality of test heads.
4 more elements
Dependencies are inferred from the claim text.