Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking

A semiconductor package comprising:

• a thin substrate having a dielectric layer, the thin substrate having a pair of longitudinal edges and a pair of lateral edges, the dielectric layer having an upper surface and lower surface;
• a plurality of bonding pads and traces disposed on the upper surface of the dielectric layer, the bonding pads locating along the longitudinal edges of the thin substrate and electrically connecting to the corresponding traces;
• a plurality of solder ball pads disposed at the lower surface of the dielectric layer;
• a plurality of vias, each connecting the solder ball pad to the corresponding bonding pad through the trace;
• a plurality of solder balls mounted on the solder ball pads for connecting to external circuits;
• a chip attached on the thin substrate, the chip having a pair of longitudinal edges and a pair of lateral edges, the chip having a plurality of chip pads electrically connected to the corresponding bonding pads, and
• a package body encapsulating the chip and the upper surface of the thin substrate;
• wherein the area surrounded by the solder balls is smaller than the area of the chip, at least one via is offset disposed under the lateral edge of the chip so as to be closer to the lateral edge, relative to adjacently arranged vias, for supporting the chip.