SRAM cell

A memory cell including an access transistor, a pull-up transistor and a pull-down transistor, comprising:

• a semiconductor substrate, wherein a first and a second conductivity type wells are formed, a first active region is defined in the well of the first conductivity type and a second active region is defined in the well of the second conductivity type, by a field oxide layer;
• a gate insulating layer formed on the first and second active regions;
• first and second gates of the access transistor and the pull-up transistor, formed on the first active region, and a third gate of the pull-down transistor formed on the second active region;
• impurity diffusion regions of the second conductivity type of the access transistor and the pull-up transistor, formed in the first active region of both sides of each of the first and second gates, wherein one of the impurity diffusion regions is a common region;
• and
• impurity diffusion regions of the first conductivity type formed of the pull-down transistor in the second active region of both sides of the third gate, said memory cell comprising a static random access memory cell (SRAM).