Thin film transistor, liquid crystal display and fabricating methods thereof

A thin film transistor circuit comprising:

• a first thin film transistor having a substrate, a first source electrode and a first drain electrode on said substrate, a buffer layer covering said source electrode and said drain electrode and a disclosed surface of the substrate, a first active layer formed on said buffer layer, wherein said first active layer has a first source region, a first channel region and a first drain region, a first gate insulating layer on said first active layer, and a first gate electrode on said first gate insulating layer;
• a second thin film transistor having the substrate, a source electrode and a drain electrode on said substrate, the buffer layer covering said source electrode and said drain electrode and the disclosed surface of the substrate, a second active layer formed on said buffer layer, wherein said second active layer has a second source region, a second channel region and a second drain region, a second gate insulating layer on said second active layer, and a second gate electrode on said second gate insulating layer;
• a first transparent conducting wire connecting said first source electrode and said first source region of said first thin film transistor;
• a second transparent conducting wire connecting said second source electrode and said second source region of said second thin film transistor;
• and
• a third connecting wire connecting said first drain electrode and said first drain region of said first thin film transistor to said second drain electrode and said second drain region of said second thin film transistor.

A liquid crystal display comprising:

• a substrate;
• a data line on said substrate;
• a buffer layer covering said data line;
• an active layer on said buffer layer, said active layer having source, channel and drain regions;
• a insulating layer covering said active layer;
• a gate electrode substantially overlapping said channel region;
• a gate line connected to said gate electrode, said gate line crossing with said data line;
• a passivation layer covering said gate electrode and said gate line;
• a first contact hole in said first, said second and said passivation layer, said first contact hole disclosing a portion of said data line;
• a second contact hole disclosing said source region;
• a third contact hole disclosing said drain region;
• a transparent conductive wire connecting said data line to said source region through said first and second contact holes;
• and
• a pixel electrode connected to said drain region through said third contact hole.

A thin film transistor, comprising:

• a substrate;
• source and drain electrodes on said substrate;
• a first buffer layer covering said source and drain electrodes and a disclosed surface of said substrate;
• an active layer on said first buffer layer, said active layer having a source region, a channel region and a drain region;
• a gate insulating layer on said active layer;
• a gate electrode on said gate insulating layer;
• a second buffer layer covering the active layer and the gate electrode;
• a first contact hole formed in said first buffer layer and said second buffer layer, said first contact hole disclosing said source electrode and source region;
• a second contact hole formed in said first buffer layer and said second buffer layer, said second contact hole disclosing said drain electrode and said drain region;
• a first conductive layer connecting said source electrode to said source region through the first contact hole, said first conductive layer being a transparent conductive layer;
• and
• a second conductive layer connecting said drain electrode to said drain region through the second contact hole, said second conductive layer being a transparent conductive layer.