Back to results
US 6,204,517 B1Granted
Single electron transistor memory array
AssigneeTexas Instruments - Acer Incorporated
InventorShye-Lin Wu
Life of this patent
Estimating the term…
Abstract
A structure of a single-electron-transistor memory array is disclosed in the present invention. A substrate is provided. A buried oxide layer is on the substrate. A plurality of silicon wires are arranged on the buried oxide layer, wherein each of the silicon wires has a pair of ends. Oxynitride layers covers on the silicon wires. A polysilicon layer covers the oxynitride layers and the buried oxide layer. A source region and a drain region connect to a first end and a second end of each of the silicon wires, respectively.
Claims4
A single-electron-transistor memory array, comprising:
- a silicon substrate;
- a buried oxide layer in a thickness about 0.3˜0.5 micrometers formed in said silicon substrate, wherein said silicon substrate has a thickness over said buried oxide layer;
- a plurality of silicon wires arranged on said buried oxide layer, each of said silicon wires having a pair of ends and said silicon wires being separated from each other, wherein the silicon wires are formed in accordance with a process comprising:
- thermal oxidizing said silicon substrate to reduce the thickness of said silicon substrate on said buried oxide layer;
- removing said thermal oxide layer;
- and
- patterning said silicon substrate on said buried oxide layer;
- an oxynitride layer having a thickness about 10˜100 angstroms formed on the surface of said silicon wires for isolation;
- and
- a polysilicon layer partially covering said oxynitride layers for perpendicularly bridging across said buried oxide layer and connecting to a gate electrode.
7 more elements
Dependencies are inferred from the claim text.