Focal plane readout unit cell induced pulse diversion circuit and method

An induced pulse diversion circuit suitable for use with a focal plane readout unit cell, comprising:

• a signal path having a gate device which controls access to said signal path in accordance with a signal applied at a control input,
• a diversion path having a gate device which controls access to said diversion path in accordance with a signal applied at a control input, and
• a diversion control circuit which receives a photocurrent at an input and is arranged to divert pulses induced in said photocurrent to said diversion path, comprising:
• an inverting amplifier having an input connected to receive said photocurrent and an output, and
• a pass device having a control input connected to receive the output of said inverting amplifier and arranged to pass said photocurrent to both of said gate devices in accordance with said inverting amplifier output,
• said inverting amplifier output connected to the control input of said diversion path gate device and arranged to open said gate device upon receipt of an induced pulse in said photocurrent to divert said pulse to said diversion path.

A focal plane readout unit cell, comprising:

• a pulse diversion circuit, comprising:
• a signal path having a gate device which controls access to said signal path in accordance with a signal applied at a control input,
• a diversion path having a gate device which controls access to said diversion path in accordance with a signal applied at a control input, and
• a diversion circuit which receives a photocurrent at an input and is arranged to divert pulses induced in said photocurrent to said diversion path, comprising:
• an inverting amplifier having an input connected to receive said photocurrent and an output, and
• a pass device having a control input connected to receive the output of said inverting amplifier and arranged to pass said photocurrent to both of said gate devices in accordance with said inverting amplifier output,
• said inverting amplifier output connected to the control input of said diversion path gate device and arranged to open said gate device upon receipt of an induced pulse in said photocurrent to divert said pulse to said diversion path;
• an integrating capacitor connected to said signal path and arranged to integrate photocurrent received by said capacitor via said signal path during an integration period, and
• a switching device connected to said integrating capacitor and arranged to read out the charge stored on said integrating capacitor at the end of said integration period.

An integrated focal plane array with induced pulse diversion circuitry, comprising:

• a plurality of focal plane readout unit cells arranged into a row and column array, each unit cell comprising:
• a pulse diversion circuit, comprising:
• a signal path having a gate device which controls access to said signal path in accordance with a signal applied at a control input,
• a diversion path having a gate device which controls access to said diversion path in accordance with a signal applied at a control input, and
• a diversion circuit which receives a photocurrent at an input and is arranged to divert pulses induced in said photocurrent to said diversion path, comprising:
• an inverting amplifier having an input connected to receive said photocurrent and an output, and
• a pass device having a control input connected to receive the output of said inverting amplifier and arranged to pass said photocurrent to both of said gate devices in accordance with said inverting amplifier output,
• said inverting amplifier output connected to the control input of said diversion path gate device and arranged to open said gate device upon receipt of an induced pulse in said photocurrent to divert said pulse to said diversion path;
• an integrating capacitor connected to said signal path and arranged to integrate photocurrent received by said capacitor via said signal path during an integration period, and
• a switching device connected to receive a timing pulse at a control input and to said integrating capacitor and arranged to read out the charge stored on said integrating capacitor at the end of said integration period in response to said timing pulse;
• clock generation circuitry arranged to generate said timing pulses to each of said switching devices in said array, and
• a plurality of column multiplexers connected to respective columns of said unit cells for assembling the charges from said array of unit cells into a video frame, said unit cells, clock generation circuitry and column multiplexers integrated together on a common substrate.