Contact and deep trench patterning
AssigneeInfineon Technologies North America Corp.
InventorsThomas S. Rupp, Alan Thomas, Franz Zach
Life of this patent
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Abstract
A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer. A semiconductor device in accordance with the invention is also included.
Claims21
A method for patterning semiconductor components comprising the steps of:
- providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer;
- patterning the mask layer to form a first group of substantially parallel lines in the mask layer;
- patterning a resist layer to form a second group of substantially parallel lines disposed perpendicular to the first group of substantially parallel lines;
- and
- etching through the dielectric layer in accordance with the resist layer and the first group of substantially parallel lines of the mask layer to form rectangular holes in the dielectric layer.
A method for patterning semiconductor components comprising the steps of:
- providing a substrate layer, the substrate layer having a dielectric layer formed thereon, a first mask layer formed on the dielectric layer and a second mask layer formed on the first mask layer, the second mask layer and the dielectric layer being selectively etchable relative to the first mask layer;
- patterning the second mask layer to form a first group of substantially parallel lines in the second mask layer;
- patterning a resist layer to form a second group of substantially parallel lines disposed perpendicular to the first group of substantially parallel lines;
- and
- etching through the first mask layer in accordance with the resist layer and the first group of substantially parallel lines of the second mask layer to form rectangular holes in the dielectric layer;
- etching the dielectric layer in accordance with the rectangular holes to form rectangular holes in the dielectric layer down to the substrate layer;
- and
- removing remaining portions of the first mask layer and the second mask layer.
A method for patterning semiconductor components comprising the steps of:
- providing a substrate layer, the substrate layer having a dielectric layer formed thereon, a first mask layer formed on the dielectric layer, the first mask layer and the dielectric layer being selectively etchable relative to each other;
- patterning a resist on the first mask layer by forming substantially parallel lines;
- etching through the first mask layer in accordance with the patterned resist to form a first group of substantially parallel lines in the first mask layer;
- removing the resist;
- patterning a second resist on the first mask layer by forming a second group of substantially parallel lines disposed substantially perpendicular to the first group of substantially parallel lines;
- etching through the dielectric layer in accordance with the patterned second resist and the first group of substantially parallel lines to form rectangular holes in the dielectric layer down to the substrate layer;
- removing the second resist;
- and
- removing remaining portions of the first mask layer.
Dependencies are inferred from the claim text.