Multiple implantation and grain growth method

A method for fabricating a semiconductor device, comprising

• forming a gate stack isolated by field oxide regions in a substrate, said gate stack having an electrical insulator layer on said substrate, a gate layer deposited on said electrical insulator layer, an implant layer deposited on said gate layer, and an electrically insulating spacer layer surrounding said gate layer and said implant layer, said implant layer being composed of a material having a plurality of grains;
• bombarding said implant layer, through an exposed surface thereon, with a source of ions to implant said implant layer with said ions at a first depth;
• rapid thermal processing said implant layer to increase the grain size of the grains in said plurality of grains in said implant layer;
• and
• bombarding said implant layer through said exposed surface with said source of ions to implant said implant layer with said ions, said ions being implanted at a second depth.

A film formation method comprising:

• forming an implant layer on a substrate, said implant having a plurality of grains therein, wherein said implant layer comprises TiSix where x≧2, wherein said TiSix is sputtered on said substrate and said substrate is composed of a material selected from the group consisting of SiO2 and polysilicon, and wherein said layer of TiSix has a thickness of about 150 Å to about 5000 Å;
• bombarding said implant layer, through an exposed surface thereon, with a source of phosphorous ions to implant said implant layer with said phosphorous ions at a first depth;
• bombarding said implant layer, through said exposed surface thereon, with said source of phosphorous ions to implant said implant layer with said phosphorous ions at a second depth greater than the first depth;
• and
• heating said implant layer to increase the grain size of the grains in said plurality of grains in said implant layer.

A method for fabricating a semiconductor device comprising:

• forming a gate stack isolated by field oxide regions in a substrate, said gate stack having an electrical insulator layer on said substrate, a gate layer disposed on said electrical insulator layer, an implant layer disposed on said gate layer, and an electrically insulating spacer layer surrounding said gate layer and said implant layer, said implant layer having a thickness of about 150 Å to about 5000 Å and being composed of TiSix, where x≧2, said TiSix having a plurality of grains therein, wherein said TiSix is sputtered on said substrate, said substrate being composed of a material selected from the group consisting of SiO2 and polysilicon;
• bombarding said implant layer, through an exposed surface thereon, with a source of phosphorous ions to implant said implant layer with said phosphorous ions at a first depth;
• bombarding said implant layer, through said exposed surface thereon, with said source of phosphorous ions to implant said implant layer with said phosphorous ions at a second depth greater than the first depth;
• and
• heating said implant layer with a plurality of rapid thermal processing anneals to increase the grain size of the grains in said plurality of grains in said implant layer.

A method for fabricating a semiconductor device, comprising

• forming an electrically conductive material situated upon a substrate;
• forming an implant layer, composed of a material having a plurality of grains therein, on said electrically conductive material;
• bombarding said implant layer, through an exposed surface thereon, with a source of ions to implant said implant layer with said ions at a first depth;
• bombarding said implant layer, through said exposed surface thereon, with said source of ions to implant said implant layer with said ions at a second depth greater than and separated from the first depth;
• forming an electrically insulting layer on said electrically conductive material and said implant layer;
• and
• rapid thermal processing said implant layer to increase the grain size of the grains in said plurality of grains in said implant layer.

A semiconductor fabrication method comprising:

• forming a pair of field oxides in a silicon substrate;
• forming a gate oxide on the silicon substrate;
• forming an electrically conductive gate layer on the gate oxide;
• forming a refractory metal silicide layer having a plurality of grain therein and situated on the electrically conductive gate layer;
• bombarding said refractory metal silicide layer, through an exposed surface thereon, with a source of ions to implant said refractory metal silicide layer with said ions at a first depth;
• bombarding said refractory metal silicide layer, through said exposed surface thereon, with a source of ions to implant said refractory metal silicide layer with said ions at a second depth that is greater than and separated from the first depth;
• rapid thermal processing said refractory metal silicide layer to increase the grain size of the grains in said plurality of grains in said refractory metal silicide layer;
• forming an electrically insulative layer on the refractory metal silicide layer;
• forming a gate stack from the gate oxide, the gate layer, the refractory metal silicide layer, and the electrically insulative layer, the gate stack having a sidewall and being situated in between that pair of field oxides;
• and
• forming an electrically insulative spacer on the sidewall of the gate stack.