Self aligned contact pad in a semiconductor device and method for forming the same
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Young Chung, Jae-Goo Lee, Chang-Hyun Cho
Life of this patent
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Abstract
Self-aligned contact pads in a semiconductor device and a method for forming the same are provided. These self-aligned contact pads can increase the upper surface of the contact pads to increase alignment margins. Portions of the gate mask are undercut, increasing the spaces between the gate structures. As a result, contact pads that are filled in these spaces have an increased upper surface contacting an electrical contact.
Claims19
A method for forming a self aligned contact pad in a semiconductor device, comprising:
- forming a plurality of stacked conductive structures over a semiconductor substrate, each of the stacked conductive structures comprising a first conductive layer, a multiple capping layer including at least stacked first, second, and third material layers, and a sidewall spacer coating the first conductive layer and the capping layer, and each of the stacked conductive structures being spaced from each other;
- forming an interlayer insulating film over the semiconductor substrate and the plurality of stacked conductive structures;
- etching the interlayer insulating film to form openings for a contact pads that expose the semiconductor substrate;
- undercutting the second material layer of the capping layer;
- filling the opening with a second conductive layer such that the second conductive layer contacts exposed portions of the semiconductor substrate;
- and
- planarizing the second conductive layer until upper surfaces of the second material layer of the capping layers are exposed to form self aligned contact pads that are electrically insulated from adjacent contact pad by the second material layer.
A method for forming a self aligned contact pad in a semiconductor device, comprising:
- forming a plurality of stacked gate structures over a semiconductor substrate having active and inactive regions, each stacked gate structure comprising a gate electrode conductive layer, a gate mask layer at least including stacked first through third material layers, and a gate spacer coating the gate electrode conductive layer and the gate mask layer, the stacked gate structures being spaced form each other;
- forming a first etch stop layer over the semiconductor substrate;
- forming a first interlayer insulating film over the first etch stop layer and the plurality of stacked gate structures;
- etching the first interlayer insulating film between pairs of the plurality of gate structures to expose voids in the first interlayer insulating layer;
- forming a second etch stop layer over the first interlayer insulating film;
- forming a second interlayer insulating film over the second etch stop layer to blanket the plurality of gate structures;
- forming a mask pattern over the second interlayer insulating film, the mask having a ‘T’ shaped opening, wherein the ‘T’ shaped opening portion includes at least two different contact regions of two storage node contact regions and one bit line contact region;
- etching the second interlayer insulating film, the second etch stop layer, the first interlayer insulating film, and the first etch stop layer, using the mask pattern, to form openings for contact pads that exposes the semiconductor substrate;
- undercutting the second material layer of the gate mask, wherein the undercutting of the mask comprises:
- etching the second interlayer insulating film until the second etch stop layer is exposed;
- undercutting the second material layer of the gate mask with wet etching in phosphoric acid;
- etching the first interlayer insulating film until the first etch stop layer is exposed;
- and
- removing the first etch stop layer;
- filling the opening with a contact pad conductive layer;
- and
- forming a contact pad by planarizing the contact pad conductive layer such that the second material layer of the gate mask is exposed.
Dependencies are inferred from the claim text.