Self-aligned extension junction for reduced gate channel
AssigneeAdvanced Micro Devices, Inc.
InventorsAllen S. Yu, Paul J. Steffan
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device having self-aligned extension junctions and a reduced gate channel length by etching an opening in a layer of phosphoro silicate glass that has been deposited on a substrate. The layer of phosphoro silicate glass serves as a self-aligned solid diffusion source to form LDD extensions. Spacers are formed on the walls of the opening in the phosphoro silicate glass and serve to reduce the length of the gate channel. A gate structure is formed by depositing a layer of gate oxide in the opening in the layer of phosphoro silicate glass and a layer of polysilicon is formed over the layer of gate oxide.
Claims10
A method of manufacturing a semiconductor device having self-aligned extension junctions and a reduced gate channel length, the method comprising:
- (a) depositing a layer of phosphoro silicate glass on a substrate;
- (b) forming a layer of photoresist on the layer of phosphoro silicate glass;
- (c) patterning the layer of photoresist with a lithographic system, wherein the photoresist is patterned with a dimension having a minimum printable size available from the lithographic system;
- (d) developing the patterned layer of photoresist forming an opening in the layer of photoresist and exposing a portion of the layer of phosphoro silicate glass;
- (e) etching the exposed portion of the layer of phosphoro silicate glass forming an opening in the layer of phosphoro silicate glass and exposing a portion of the substrate, wherein remaining portions of the layer of phosphoro silicate glass form self-aligning solid diffusion sources for a formation of LDD extensions;
- (f) forming spacers on walls of the opening in the layer of phosphoro silicate glass, wherein the spacers reduce a length of a gate structure to be formed and reduces an overlapping capacitance in the semiconductor device by offsetting the diffusion of ions used to form the LDD extensions;
- (g) forming the LDD extensions in the substrate;
- (h) forming the gate structure;
- and
- (i) forming S/D junctions, wherein the gate structure is formed by:
- (j) forming a layer of high quality gate oxide on an exposed surface of the substrate in the opening formed in the layer of phosphoro silicate glass;
- (k) depositing a blanket layer of polysilicon;
- (l) forming a photoresist gate mask on the blanket layer of polysilicon exposing portions of the blanket layer of the polysilicon;
- (m) etching exposed portions of the blanket layer of polysilicon exposing portions of the underlying layer of phosphoro silicate glass;
- and
- (n) removing the photoresist gate mask.
Dependencies are inferred from the claim text.