Method of fabricating a capacitor with a low-resistance electrode structure in integrated circuit

A method for fabricating a capacitor in an integrated circuit, comprising the steps of:

• preparing a semiconductor substrate;
• forming a first electrode over the substrate;
• forming a first dielectric layer covering the first electrode;
• and
• forming a second electrode over the first dielectric layer above the first electrode;
• and the second electrode being composed of a doped polysilicon layer over the first dielectric layer, a metal silicide layer over the doped polysilicon layer, and a second dielectric layer over the metal silicide layer, wherein the second dielectric layer is formed with same material and has a same thickness as the first dielectric layer.

A method for fabricating a capacitor in an integrated circuit, comprising:

• forming a first electrode over a substrate;
• forming a first dielectric layer over the substrate covering the first electrode, wherein the first dielectric layer also serves as an etching end point;
• forming a second electrode over the first dielectric layer above the first electrode, wherein the second electrode comprises a doped polysilicon layer and a metal silicide layer, and the second electrode is covered by a second dielectric layer which also serves as an etching end point;
• forming a planarized insulating layer over the first dielectric layer and the second dielectric layer;
• etching at selective sites of the insulating layer until a part of the insulating layer and the underlying first dielectric layer and the second dielectric layer are removed to form contact windows.