Method for fabricating a polycide semiconductor device
AssigneeLG Semicon Co., Ltd.
InventorJong Wan Jung
Life of this patent
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Abstract
A method for fabricating a semiconductor device includes the steps of forming a field oxide layer on a field region of a semiconductor substrate where a field region and an active region are defined, forming a polycide layer on the entire surface of the semiconductor substrate including the field oxide layer and selectively removing the polycide layer to form a gate electrode and a lower electrode of a capacitor, successively forming a dielectric layer and a polysilicon layer on the entire surface including the lower electrode of the capacitor and patterning the dielectric layer and the lower electrode to form an upper electrode pattern and a resistor pattern, and forming an insulating layer to cover the resistor pattern and forming another polycide layer on the upper electrode of the capacitor.
Claims15
A method for fabricating a semiconductor device on a semiconductor substrate, the method comprising the steps of:
- forming a field oxide layer on a field region of the semiconductor substrate;
- forming a first polycide layer on the entire surface of the semiconductor substrate including the field oxide layer;
- selectively removing the first polycide layer, thereby forming a gate electrode and a lower electrode of a capacitor;
- successively forming a dielectric layer and a polysilicon layer on the entire surface including the lower electrode of the capacitor and patterning the dielectric layer and the lower electrode to form an upper electrode pattern of the capacitor and a resistor pattern;
- and
- forming an insulating layer on the resistor pattern;
- forming a second polycide layer on the upper electrode pattern of the capacitor.
A method for fabricating a semiconductor device on a semiconductor substrate, the method comprising the steps of:
- forming a field oxide layer on the semiconductor substrate;
- forming a first polysilicon layer and a first metal layer on the entire surface including the field oxide layer so as to form a first polycide layer on the first polysilicon layer by an annealing process;
- selectively etching the first polysilicon layer and the polycide layer to form a gate electrode and a lower electrode of a capacitor;
- forming a dielectric layer and a second polysilicon layer on the entire surface including the lower electrode of the capacitor and then successively removing the dielectric layer and the second polysilicon layer to form an upper electrode pattern of the capacitor and a resistor pattern;
- forming an insulating layer to cover the resistor pattern and forming sidewall spacers on both sides of the upper electrode pattern of the capacitor;
- and
- forming a second metal layer on the entire surface including the upper electrode pattern of the capacitor so as to form a second polycide layer on the semiconductor substrate at both sides of the gate electrode and on the upper electrode pattern of the capacitor by an annealing process.
A method for fabricating a semiconductor device on a semiconductor substrate, the method comprising the steps of:
- forming a field oxide layer on the semiconductor substrate;
- forming a first polysilicon layer and a first metal layer on the entire surface including the field oxide layer so as to form a first polycide layer on surface of the first polysilicon layer by an annealing process;
- selectively removing the first polysilicon layer and the polycide layer to form a gate electrode and a lower electrode of a capacitor;
- successively forming a dielectric layer and a second polysilicon layer on the entire surface including the lower electrode of the capacitor and then selectively removing the second polysilicon layer to form an upper electrode pattern of the capacitor and a resistor pattern;
- forming an insulating layer to cover the resistor pattern so as to form sidewall spacers on both sides of the upper electrode pattern of the capacitor;
- and
- depositing and then annealing a second metal on the entire surface including the upper electrode pattern of the capacitor so as to form a second polycide layer on surface of the upper electrode pattern of the capacitor.
Dependencies are inferred from the claim text.