US 6,204,074 B1 · Chip design process for wire bond and flip-chip package

Abstract

A method of fabrication are provided in which permanent external electrical connection to active circuitry in a semiconductor structure can be made through either a wire bond pad or metal bump formed thereon. A final metallization including a wire bond pad is disposed over and electrically connected with the active circuitry. An insulating material film is disposed over the final metallization leaving the wire bond pad and a portion of the final metallization laterally displaced from the pad exposed. A metal bump contacts the laterally displayed exposed portion of the final metallization. The wire bond pad is electrically coupled with and laterally displaced from the metal bump through the final metallization. The metal bump and wire bond pad are configured to facilitate electrical connection of the semiconductor structure with an external connector, such as a modular packaging substrate. The structure may also be used for testing and burning in a semiconductor die without direct physical contact of the external testing device to the wire bond pad.

Claims20

Dependent claims

A method for fabricating a semiconductor die that combines two different exposed electrical contacts and facilitates electrical connection of an external connector to at least one of said exposed electrical contacts, said method comprising the steps of:

(a) providing a semiconductor substrate with a region of active circuitry;
(b) forming a metallization over said semiconductor substrate, said metallization electrically coupled to said region of active circuitry;
(c) forming an insulating material over said metallization;
(d) defining a first contact hole in said insulating material to form an exposed planar wire bond pad of said metallization, wherein when processing of said semiconductor die is complete said exposed planar wire bond pad of said metallization is exposed to facilitate wire bond connection of the external connector comprising an external wiring to the exposed planar wire bond pad;
and
(e) defining a second contact hole laterally displaced from said first contact hole in said insulating material, said second contact hole exposing a portion of said metallization laterally displaced from and electrically connected to said exposed planar wire bond pad, and forming a metal bump in said second contact hole, said metal bump contacting said exposed portion of said metallization and being disposed above said region of active circuitry of the semiconductor die, wherein electrical connection to said semiconductor substrate can occur through either said exposed planar wire bond pad or said metal bump.

3 more elements

(a) providing a semiconductor substrate with a region of active circuitry;
(b) forming a metallization over said semiconductor substrate, said metallization electrically coupled to said region of active circuitry;
(c) forming an insulating material over said metallization;
(d) defining a first contact hole in said insulating material to form an exposed planar wire bond pad of said metallization, wherein when processing of said semiconductor die is complete said exposed planar wire bond pad facilitating electrical and mechanical connection of an external wiring to and directly with said exposed planar wire bond pad of said metallization;
and
(e) defining a second contact hole laterally displaced from said first contact hole in said insulating material, said second contact hole exposing a portion of said metallization laterally displaced from and electrically connected to said exposed planar wire bond pad, and forming a metal bump in said second contact hole, said metal bump contacting said exposed portion of said metallization and being disposed above said region of active circuitry of the semiconductor die, wherein electrical connection to said semiconductor substrate can occur through either said exposed planar wire bond pad or said metal bump.

3 more elements

(a) providing a semiconductor substrate with a region of active circuitry;
(b) forming a first metallization over said semiconductor substrate, said first metallization electrically coupled to said region of active circuitry;
(c) forming an insulating material over said first metallization;
(d) defining a first contact hole in said insulating material and a second contact hole in said insulating material laterally displaced from said first contact hole, wherein electrical connection to said semiconductor substrate can occur through either said first or second contact holes;
and
(e) forming a second metallization over said first metallization in at least one of said first contact hole and said second contact hole wherein said second contact hole has at least one different metallization composition from that of said first contact hole over said first metallization of said second contact hole and wherein said second contact hole has at least one metallization layer over said first metallization and said first metallization of said first contact hole is exposed.

3 more elements

Dependencies are inferred from the claim text.

Chip design process for wire bond and flip-chip package

Life of this patent

Chip design process for wire bond and flip-chip package

Life of this patent

Abstract

Claims20