Programmable digital signal processor integrated circuit device and method for designing custom circuits from same

A programmable system, comprising:

• a) a communications bus;
• b) a plurality of programmable apparatus which interface with said communications bus, each said apparatus comprising,
• 1) a plurality of programmable signal processor means having means for receiving and storing parameters and microinstructions, and means for executing microinstructions, each said programmable signal processor means for performing an operation according to said microinstructions and said parameters on signal data received by said programmable signal processor means;
• 2) a core means comprising interface means for interfacing with said communications bus, processing means for distinguishing between at least topological and parametric data received by said core means over said communications bus, and matrix switching means for interconnecting at least two of said plurality of programmable signal processor means in a desired manner in response to said topological data received over said communications bus;
• and
• 3) a plurality of data bus means for connecting said plurality of programmable signal processor means to said matrix switching means;
• and
• 4) at least one third bus means coupled to said core means and to said means for receiving and storing for transmitting said parametric data and said microinstructions to said means for receiving and storing of a plurality of said programmable signal processor means;
• c) linkage means coupled to said at least two of said plurality of programmable apparatus, for carrying signal data and timing signals between the same.

A method for designing a custom programmable apparatus, said apparatus interfacing with a communications bus and having a plurality of programmable signal processor means which are programmed with parameters and microinstructions for controlling and performing operations on received signal data, a core means capable of interfacing with said communications bus, of distinguishing between at least topological, signal, and at least one of parametric and microinstruction data received by said core means over said communications bus, and of interconnecting at least two of said plurality of programmable signal processor means via a plurality of signal data bus means in a desired manner, and at least one third bus means for carrying parametric information and microinstruction information from said core means to said programmable signal processor means, said method comprising:

• a) determining suitable interconnections of said plurality of said programmable signal processor means and said signal data bus means for accomplishing desired functions on data flowing therethrough;
• b) determining suitable parameters and microinstructions for said programmable signal processor means;
• c) arranging said core means by coding said determined suitable interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections;
• and
• d) providing said determined suitable parameters and microinstructions for said programmable signal processor means to said programmable signal processor means by coding said suitable parameters into second code and forwarding said second code via said communications bus, said core means, and said at least one said third bus means to a desired programmable signal processor means.

A method for designing a custom apparatus having a plurality of functional block means having desired parameters for performing desired operations on received signal data, and means for interconnecting in a desired manner at least two of said plurality of functional block means, said method comprising:

• a) obtaining a programmable apparatus which interfaces with a communications bus, said apparatus having a plurality of programmable signal processor means for performing operations on received signal data, a core means capable of interfacing with said communications bus and of interconnecting at least two of said plurality of programmable signal processor means in a desired manner, a plurality of signal data bus means for carrying said signal data, and at least one third bus means for obtaining and carrying parametric data and microinstruction data to said programmable signal processor means;
• b) in conjunction with a processor coupled to at least said communications bus, determining suitable interconnections of said plurality of programmable signal processors of said programmable apparatus, and determining suitable parameters and microinstructions for said programmable signal processor means of said programmable apparatus;
• c) arranging said core means of said programmable apparatus by coding said determined suitable interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections;
• d) providing said determined suitable parameters and suitable microinstructions to said programmable signal processor means of said programmable apparatus by coding said suitable parameters and microinstructions into second code and forwarding said second code via said at least one third bus to a desired programmable signal processor means of said programmable apparatus;
• e) testing said programmable apparatus to determine whether said programmable apparatus is suitable for performing said desired operations;
• f) finalizing core interconnection design, and finalizing said parameter values and microinstructions for said programmable signal processor means;
• and
• g) producing integrated circuits based on said finalized interconnection design and based on said parameter values and microinstructions, said integrated circuits having at least a plurality of functional block means functionally equivalent to those programmable signal processor means utilized in said finalizing step, said functional block means having said finalized parameter values.

A programmable apparatus comprising:

• a) a communications bus for transmitting signal data, parameters, and microinstructions from a host;
• b) at least one programmable signal processor means having means for receiving and storing said parameters and microinstructions, means for executing microinstructions, and control output means for outputting signals indicating the state of said programmable signal processor means, said programmable signal processor means for performing an operation according to said microinstructions and said parameters on said signal data received by said programmable signal processor means;
• c) a core means comprising processing means for distinguishing between at least signal and parametric data received by said core means over said communications bus, intelligent buffer means for interfacing with said communications bus, for receiving said parametric data, for receiving said signals from said control output means, and for outputting said parametric data in response to said signals from said control output means;
• d) at least one data bus means for coupling said communications bus to said programmable signal processor means via said core means and transmitt ing signal data thereover;
• and
• e) at least one third bus means coupling said intelligent buffer means to said means for receiving and storing parameters and microinstructions, for transmitting said parameters and microinstructions thereover.

A programmable apparatus for interfacing with a communications bus, said apparatus comprising:

• a) a plurality of functional block means, each said functional block means for performing an operation on signal data received by said functional block means;
• b) a core means comprising interface means for interfacing with said communications bus, processing means for distinguishing between at least topological and parametric data received by said core means over said communications bus, matrix switching means for interconnecting at least two of said plurality of functional block means in a desired manner in response to said topological data received over said communications bus, wherein parametric data received by said processing means is sent by said processing means via a parametric bus to at least a first of said functional block means to control internal parameters of a least said first of said functional block means, and wherein signal data is received by said plurality of functional block means via data busses coupled to said matrix switching means;
• c) said plurality of data bus means;
• and
• d) said parametric bus.

A programmable system, comprising:

• a) a communications bus;
• b) a plurality of programmable apparatus, each said programmable apparatus capable of interfacing with said communication bus, and each said programmable apparatus comprising,
• 1) a plurality of functional block means, each said functional block means for performing an operation on signal data received by said functional block means,
• 2) a core means comprising interface means for interfacing with said communications bus, processing means for distinguishing between at least topological and parametric data received by said core means over said communications bus, matrix switching means for interconnecting at least two of said plurality of functional block means in a desired manner in response to said topological data received over said communications bus, wherein parametric data received by said processing means is sent by said processing means via a parametric bus to at least a first of said functional block means to control internal parameters of a least said first of said functional block means and wherein signal data is received by said plurality of functional block means via data busses coupled to said matrix switching means,
• 3) said plurality of data bus means, and
• 4) said parametric bus;
• and
• c) linkage means for connecting at least two of said plurality of programmable apparatus.

A method for designing a custom programmable apparatus, said apparatus interfacing with a communications bus and having a plurality of functional block means having parameters for performing operations on received signal data, a core means for interfacing with said communications bus, for distinguishing between at least topological, signal, and parametric data received by said core means over said communications bus, and for signal flow interconnecting at least two of said plurality of functional block means in a desired manner, and a parametric bus means for carrying parametric information from said core means to said functional block means, said method comprising:

• a) determining suitable signal flow interconnections of said plurality of functional blocks;
• b) determining suitable parameters for said functional block means;
• c) arranging said core means by coding said determined suitable signal flow interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections;
• and
• d) providing said determined suitable parameters for said functional block means to said functional block means by coding said suitable parameters into second code and forwarding said second code via said communications bus, said core means and said parametric bus to a desired functional block means.

A method for designing a custom integrated circuit apparatus having a plurality of functional block means having desired parameters for performing desired operations on received signal data, and a core means interconnecting in a desired manner at least two of said plurality of functional block means for a desired sequential flow of signal data, said method comprising:

• a) obtaining a programmable apparatus which interfaces with a communications bus, said apparatus having a plurality of functional block means for performing operations on received signal data, a core means for interfacing with said communications bus and for signal flow interconnecting at least two of said plurality of functional block means in a desired manner, and a parametric bus means for obtaining and carrying parametric data to said functional block means;
• b) in conjunction with a host coupled to at least said communications bus and said programmable apparatus, determining suitable interconnections of said plurality of functional blocks of said programmable apparatus, and determining suitable parameters for said functional block means of said programmable apparatus;
• c) arranging said core means of said programmable apparatus by coding said determined suitable interconnections into first code and forwarding said first code via said communications bus to said core means to cause said core means to assume said determined suitable interconnections;
• d) providing said determined suitable parameters for said functional block means to said functional block means of said programmable apparatus by coding said suitable parameters into second code and forwarding said second code via said parametric bus to desired functional block means of said programmable apparatus;
• e) testing said programmable apparatus to determine whether said programmable apparatus is suitable for performing said desired operations;
• f) finalizing core interconnection design and parameter values for said functional block means;
• and
• g) producing integrated circuits based on said finalized interconnection design and based on said parameter values, said integrated circuit's having at least a plurality of interconnected functional block means having said finalized parameter values which are functionally equivalent to those functional block means utilized in said finalizing step.