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AssigneeMotorola, Inc.
InventorsHunter Ledbetter Scales, III, Keith Everett Diefendorff, Brett Olsson, Pradeep Kumar Dubey, Ronald Ray Hochsprung, Bradford Byron Beavers, Bradley G. Burgess, Michael Dean Snyder, Cathy May, Edward John Silha
Estimating the term…
A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).
In a data processing system having a first memory and a second memory at a lower hierarchical level than the first memory, a data processor for prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba+(s*i)), and i is an index having a value from 0 to (n−1), the data processor comprising:
In a data processing system having a plurality of architectural registers adapted for storing a like plurality of vectors, a first, non-architected memory and a second memory at a lower hierarchical level than the first memory, a method for explicitly prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba+(s*i)), and i is an index having a value from 0 to (n−1), the method comprising the steps of:
In a data processing system having a first memory and a second memory at a lower hierarchical level than the first memory, a method for prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba +(s*i)), and i is an index having a value from 0 to (n−1), the method comprising the steps of:
In a data processing system having a first memory and a second memory at a lower hierarchical level than the first memory, a method for prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba+(s*i)), and i is an index having a value from 0 to (n−1), the method comprising the steps of:
In a data processing system having a plurality of architectural registers adapted for storing a like plurality of vectors, a first, non-architected memory and a second memory at a lower hierarchical level than the first memory, a method for explicitly prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba+(s*i)), and i is an index having a value from 0 to (n−1), the method comprising the steps of:
In a data processing system having a first memory and a second memory at a lower hierarchical level than the first memory, a method for prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba +(s*i)), and i is an index having a value from 0 to (n−1), the method comprising the steps of:
In a data processing system having a first memory and a second memory at a lower hierarchical level than the first memory, a method for prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba +(s*i)), and i is an index having a value from 0 to (n−1), the method comprising the steps of:
Dependencies are inferred from the claim text.