Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator

A transceiver circuit of the type adapted to interface between highspeed serial data signals at a 1.06 GHz data rate, and 10-bit parallel encoded transmission character bytes, the transceiver circuit comprising:

• a transmitter section for encoding a 10-bit parallel encoded transmission character byte to a serial datastream, the transmitter section having a 10-bit wide parallel input and a serial output;
• a receiver section for converting a serial datastream into a 10-bit parallel encoded transmission character byte, the receiver section having a serial input and a 10-bit parallel output;
• a multiplexer, connected to receive a 10-bit wide transmission character at a first input, the multiplexer connected to output 10-bit wide parallel data to the transmitter parallel input;
• a pattern generator, configured to generate 10-bit wide parallel data patterns in accordance with an 8B/10B transmission protocol sequence, the pattern generator comprising a linear array of eight series-connected sequential D-flip flops, each flip flop including a Q output, wherein each Q output of the linear array of D-flip flops defines a particular bit of a 10-bit wide parallel data word, the Q outputs of the first and fifth D-flip flops defining 2-bits, respectively, of the 10-bit wide parallel data word the pattern generator providing said parallel data to a second input of the multiplexer, the multiplexer operatively responsive to a mode signal to select either 10-bit wide transmission character data or 10-bit wide data patterns for outputting to the transmitter parallel input;
• and
• a signature analyzer connected in parallel fashion to the parallel data output of the receiver section,
• wherein the transmitter section serial output is coupled in feed-back fashion to the receiver section serial input, the multiplexer selecting 10-bit wide data patterns from the pattern generator for outputting to the transmitter parallel input in response to the mode signal being in an asserted condition, the transmitter serializing and transmitting the data patterns to the receiver at a characteristic operation frequency, the receiver section receiving and deserializing said data patterns into 10-bit wide parallel data, the signature analyzer sampling the 10-bit wide data patterns and returning a positive match indication signal if the last received 10-bit wide data pattern matches the last transmitted 10-bit wide data pattern generated by the pattern generator.