Semiconductor memory having improved register array access speed

A semiconductor memory, comprising:

• a memory cell array including a plurality of memory cells arranged into rows and columns;
• a register array section having a plurality of register arrays arranged into rows and columns, the number of register array rows and columns being a predetermined ratio of the number memory cell array rows and columns;
• a transfer bus coupled between the memory cell array and the register array section;
• a plurality of first switches coupled between the register arrays and the transfer bus;
• a plurality of second switches coupled to the register arrays;
• a plurality of third switches, each third switch being commonly coupled between the second switches of the same register array column and a read/write bus;
• a connection circuit that connects the transfer bus to a local read/write bus that is coupled to the read/write bus.

A semiconductor memory, comprising:

• a memory cell array having a plurality of memory cells arranged into a predetermined number of rows and columns;
• at least one register array having a plurality of registers arranged into rows and columns, the number of registers in the rows and columns being a predetermined ratio of the number of memory cells in the rows and columns in the memory cell array;
• a first transfer bus coupled between the memory cell array and the at least one register array;
• a second transfer bus coupled between the at least one register array and a non-local read/write bus;
• a local read/write bus coupled between the first transfer bus and the non-local read/write bus;
• and
• a control circuit that transfers first read data from the memory cell array to the non-local read/write bus through the first transfer bus and the local read/write bus, and at essentially the same time, transfers second read data to the at least one register array through the first transfer bus.