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US 6,200,121 B1Granted
Process for concurrently molding semiconductor chips without void and wire weep and molding die used therein
AssigneeNEC Corporation
InventorHisayuki Tsuruta
Life of this patent
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Abstract
A molding die used for concurrently packaging semiconductor chips in a large piece of synthetic resin has a cavity rectangular in cross section and having two long peripheral lines and two short peripheral lines for accommodating a circuit panel where the semiconductor chips are mounted, melted synthetic resin is supplied through a gate extending along one of the long peripheral lines to the cavity so that the melted synthetic resin smoothly flows over the cavity, and the smooth flow prevents the molded product from voids and a wire weep.
Claims17
A molding die for packaging semiconductor chips in a piece of synthetic resin, comprising:
- a die block defining
- a cavity having peripheral lines running substantially parallel to at least one side of said cavity, and accommodating said semiconductor chips mounted on a circuit panel;
- a gate open to said cavity along at least a portion of one of said peripheral lines and connected to a source of melted synthetic resin for supplying said melted synthetic resin into a vacant space of said cavity over a single surface of said circuit panel to which said semiconductor chip are mounted, through said one of said peripheral lines;
- and
- a dummy cavity in fluid communication with said cavity to receive a waste portion of said melted synthetic resin that flows out from said cavity, wherein said dummy cavity has a inner wall that inhibits the flow of said waste material out of said dummy cavity.
2 more elements
Dependencies are inferred from the claim text.