US 6,199,182 B1 · Probeless testing of pad buffers on wafer

Abstract

The input and output buffers and related peripheral circuits, such as holding circuits and ESD circuits, of an integrated circuit are tested using the boundary scan paths and three additional test bond pads. This structure provides for testing these circuits without the need physically to contact the functional bond pads. For an output buffer, one switch opens the connection between the output of the functional circuits and the input of the output buffer. A second switch connects the first test bond pad to the input of the output buffer. A third switch connects the second test bond pad to the output of the output buffer. A fourth switch connects the third test bond pad to the output of the output buffer. For an input buffer, separate first and second switches respectively connect the second and third test bond pads to the input of the input buffer. A third switch connects the first test bond pad to the output of the input buffer.

Claims31

Dependent claims

A semiconductor body having at least one integrated circuit formed at a surface thereof, the at least one integrated circuit comprising:

core functional logic;
a terminal buffer coupled in a signal path between the core functional logic and a terminal pad, for forwarding a signal along the signal path;
a load test switch for selectively connecting a load terminal to the signal path between the terminal buffer and the terminal pad and free of the terminal pad;
a first test switch for selectively connecting an input of the terminal buffer to a first test terminal;
a second test switch for selectively connecting an output of the terminal buffer to a second test terminal;
and
control circuitry for controlling the operation of the load test switch and the first and second test switches so as to be open in normal operation, and so as to be selectively closed in a test mode.

4 more elements

A method of testing output circuitry of an integrated circuit, the output circuitry including an output buffer having an input coupled to core functional circuitry and an output coupled to a terminal pad, comprising the steps of:

disconnecting the input of the output buffer from the core functional circuitry;
connecting the input of the output buffer to a first test terminal;
connecting the output of the output buffer to a second test terminal;
applying a test input signal at a first logic level to the first test terminal, for receipt by the input of the output buffer;
measuring, at the second test terminal, the drive strength of the output buffer in response to the test input signal at the first logic level;
applying a test input signal at a second logic level to the first test terminal, for receipt by the input of the output buffer;
and
measuring, at the second test terminal, the drive strength of the output buffer in response to the test input signal at the second logic level.

5 more elements

A method of testing input circuitry of an integrated circuit, the input circuitry including an input buffer having an input coupled to a terminal pad and an output coupled to core functional circuitry, comprising the steps of:

connecting the input of the input buffer to a first test terminal;
connecting the output of the input buffer to a second test terminal;
applying a test input signal at a first logic level to the first test terminal, for receipt by the input of the input buffer;
measuring, at the second test terminal, the response of the input buffer to the applying step.

1 more element

Dependencies are inferred from the claim text.

Probeless testing of pad buffers on wafer

Life of this patent

Probeless testing of pad buffers on wafer

Life of this patent

Abstract

Claims31