Circuit and method for pre-erasing/erasing flash memory array
AssigneeAMIC Technology Corporation
InventorsKou-Su Chen, Shih-Chun Fu, Jui-Te Chan
Life of this patent
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Abstract
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
Claims18
A method of slowing down erase speeds of fast discharge flash cells in a memory array, such fast discharge flash cells being characterized by erase speeds substantially faster than target erase speeds for flash cells in said array, the method comprising:
- (a) generating a conditioning signal to remove a quantity of charge from the flash cells, said quantity of charge being related to an erase speed of the flash cell and further being insufficient to place such flash cells into an erased state;
- and
- (b) applying said conditioning signal to such flash cells while such cells are in a non-erased state;
- wherein an erase speed of such fast discharge flash cells is reduced.
A control circuit for slowing down erase speeds of fast discharge flash cells in a memory array, such fast discharge flash cells being characterized by erase speeds substantially faster than target erase speeds for flash cells in said array, the circuit comprising:
- (a) a pre-erase signal generator for generating a flash cell pre-erase signal to be applied to the flash cells;
- (b) a pre-erase signal magnitude control circuit for generating a plurality of control signals, said control signals configuring a magnitude for said pre-erase signal;
- (c) a pre-erase voltage supply circuit for generating a negative voltage source;
- (d) a pre-erase voltage supply switching circuit for generating a pre-erase voltage supply signal that is based on said negative voltage source;
- (e) a pre-erase voltage supply switching control circuit configured to control gating of said pre-erase voltage supply switching circuit with a stepping signal such that said pre-erase voltage supply signal is generated as a function of said plurality of control signals and in a time sequence determined by said pre-erase signal magnitude control circuit;
- and
- wherein said flash cell pre-erase signal is configured to remove a quantity of charge from the flash cells in preparation for an erase operation, said quantity of charge being related to an erase speed of the flash cell and further being insufficient to place such flash cells into an erased state.
A control circuit for slowing down erase speeds of fast discharge flash cells in a memory array, such fast discharge flash cells being characterized by erase speeds substantially faster than target erase speeds for flash cells in said array, the circuit comprising:
- (f) a pre-erase signal generator for generating a flash cell pre-erase signal to be applied to the flash cells;
- and
- (g) a pre-erase signal magnitude control circuit for generating a plurality of control signals, said control signals configuring a magnitude for said pre-erase signal;
- (h) a pre-erase voltage supply circuit for generating a negative voltage source;
- (i) a pre-erase voltage supply switching circuit for generating a pre-erase voltage supply signal that is based on said negative voltage source;
- (j) a pre-erase voltage supply switching control circuit configured to control gating of said pre-erase voltage supply switching circuit with a stepping signal such that said pre-erase voltage supply signal is generated as a function of said plurality of control signals and in a time sequence determined by said pre-erase signal magnitude control circuit;
- wherein said flash cell pre-erase signal is configured to remove a quantity of charge from the flash cells in preparation for an erase operation, said quantity of charge being related to an erase speed of the flash cell and further being insufficient to place such flash cells into an erased state;
- further wherein said pre-erase signal generator includes a plurality of FETs connected in parallel and that are activated by said plurality of control signals to effectuate said magnitude and said duration of said pre-erase signal.
A control circuit for slowing down erase speeds of fast discharge flash cells in a memory array, such fast discharge flash cells being characterized by erase speeds substantially faster than target erase speeds for flash cells in said array, the circuit comprising:
- (a) a pre-erase signal generator for generating a flash cell pre-erase signal to be applied to the flash cells;
- and
- (b) a pre-erase signal magnitude control circuit for generating a plurality of control signals, said control signals configuring a magnitude for said pre-erase signal;
- (c) a pre-erase voltage supply circuit for generating a negative voltage source;
- (d) a pre-erase voltage supply switching circuit for generating a pre-erase voltage supply signal that is based on said negative voltage source;
- (e) a pre-erase voltage supply switching control circuit configured to control gating of said pre-erase voltage supply switching circuit with a stepping signal such that said pre-erase voltage supply signal is generated as a function of said plurality of control signals and in a time sequence determined by said pre-erase signal magnitude control circuit;
- wherein said flash cell pre-erase signal is configured to remove a quantity of charge from the flash cells in preparation for an erase operation, said quantity of charge being related to an erase speed of the flash cell and further being insufficient to place such flash cells into an erased state;
- further wherein said control signals are varied during said time sequence so that said magnitude of said pre-erase signal is varied during said defined time sequence.
A control circuit for slowing down erase speeds of fast discharge flash cells in a memory array, such fast discharge flash cells being characterized by erase speeds substantially faster than target erase speeds for flash cells in said array, the circuit comprising:
- (f) a pre-erase signal generator for generating a flash cell pre-erase signal to be applied to the flash cells;
- and
- (g) a pre-erase signal magnitude control circuit for generating a plurality of control signals, said control signals configuring a magnitude for said pre-erase signal;
- (h) a pre-erase voltage supply circuit for generating a negative voltage source;
- (i) a pre-erase voltage supply switching circuit for generating a pre-erase voltage supply signal that is based on said negative voltage source;
- (j) a pre-erase voltage supply switching control circuit configured to control gating of said pre-erase voltage supply switching circuit with a stepping signal such that said pre-erase voltage supply signal is generated as a function of said plurality of control signals and in a time sequence determined by said pre-erase signal magnitude control circuit;
- wherein said flash cell pre-erase signal is configured to remove a quantity of charge from the flash cells in preparation for an erase operation, said quantity of charge being related to an erase speed of the flash cell and further being insufficient to place such flash cells into an erased state;
- further wherein said pre-erase signal is first pre-charged to a target reference voltage level before said plurality of control signals.
Dependencies are inferred from the claim text.