Buck and boost switched capacitor gain stage with optional shared rest state

A switched capacitor array circuit having an input connected to an input node and an output connected to an output node, said array circuit comprising:

• N number of capacitors, where N is at least two;
• switching circuitry coupled to the capacitors;
• and
• a controller coupled to the switching circuitry and configured to switch the array circuit between first and second states so as to provide a first voltage gain Gsc, between third and fourth states so as to provide a second voltage gain Gsc and between fifth and sixth states so as to provide a third voltage gain Gsc, with the first, second and third voltage gains being different and with the first, third and fifth being a common state where the N number of capacitors are connected intermediate the input node and the output node.

A switched capacitor array circuit coupled to an input node and an output node, said array circuit comprising:

• a first capacitor having first and second terminals;
• switching circuitry including a first switch coupled intermediate the second terminal of the first capacitor and a third node, a second switch coupled intermediate the second terminal of the first capacitor and the input node, a third switch coupled intermediate the second terminal of the first capacitor and the output node, a fourth switch coupled intermediate the first terminal of the first capacitor and the input node and a fifth switch coupled intermediate the first terminal of the first capacitor and the output node;
• and
• a controller coupled to the switching circuitry and configured to switch the array circuit between a first state where the first capacitor is connected intermediate the input and output nodes and a second state where the second terminal of the first capacitor is connected to one of the input and output nodes and the second terminal is connected to the third node.

A switched capacitor array circuit having an input coupled to an input node and an output coupled to an output node, said array circuit comprising:

• N number of capacitors, where N is at least two;
• and
• switching circuitry coupled to the capacitors;
• and
• a controller configured to switch the array circuit between a common state and a first gain state and between the common state and a second gain state different from the first gain state, with the N number of capacitors each having a first terminal coupled to the output node when in the common state and wherein in the first state, X number of the capacitors are connected in series with one another between the input node and the output node, where X may range from one to N, and wherein in the second gain state, Y number of the capacitors are connected in series with one another between the input and the output nodes, where Y ranges from one to N and is different than X.

A switched capacitor array circuit comprising:

• N number of capacitors, where N is at least two;
• switching circuitry for switching the array circuit;
• and
• a controller coupled to the switching circuitry and configured to switch array circuit between a common state and a first gain state and between the common state and a second gain state different from the first gain state, with the N number of capacitors being connected in parallel between an input node and an output node in the common state and wherein in the first gain state, X number of capacitors are connected in series with one another, where X may range from one to N, and wherein in the second gain state, Y number of capacitors are connected in series with one another, where Y ranges from one to N.

A method of controlling a capacitor array circuit coupled between an input node and an output node and which includes N number of capacitors, wherein N is at least two, said method comprising:

• switching the array to a common state, with all N capacitors having terminals connected to the output node, so that a voltage drop across the N capacitors is the same;
• switching the array from the common state to a first gain state, which provides a voltage gain greater than one, where X number of capacitors are connected in series, with X ranging from one to N;
• switching the array from the first gain state back to the common state;
• and
• switching the array from the common state to a second gain state, which provides a voltage gain less that the voltage gain of the first gain state, where Y number of capacitors are connected in series, with Y ranging from one to N.

A switched capacitor array circuit coupled to an input node and a output node, said array circuit comprising:

• a first capacitor having first and second terminals;
• switching circuitry including a first switch coupled intermediate the second terminal of the first capacitor and a third node, a second switch coupled intermediate the second terminal of the first capacitor and the output node, a third switch coupled intermediate the first terminal of the first capacitor and the input node;
• and
• a controller coupled to the switching circuitry and configured to control a state of the switches, and wherein, in at least one of the states, the first capacitor is connected between the input and output nodes by the switching circuitry.

A switched capacitor array circuit having an input coupled to an input node and an output coupled to an output node, said switched capacitor array comprising:

• N number of unit cells, where each of the unit cells includes a capacitor and first through fifth switches, with the first switch connected directly between a second terminal of the capacitor and a third node, with the second switch connected directly between the second terminal of the capacitor and the input node, with the third switch connected directly between the second terminal of the capacitor and the output node, with the fourth switch connected directly between the first terminal of the capacitor and the input node and the fifth switch connected directly between the first terminal of the capacitor and the output node;
• a connect switch connecting the first terminal of the capacitor of one of the cells to the second terminal of the capacitor of an adjacent one of the cells;
• and
• a controller coupled to and configured to control the state of the switches of the cells and the connect switch.

A switched capacitor array circuit coupled to an input node and a output node, said array circuit comprising:

• a first capacitor having first and second terminals;
• switching circuitry including a first switch coupled intermediate the second terminal of the first capacitor and the input node, a second switch coupled intermediate the second terminal of the first capacitor and the output node, a third switch coupled intermediate the first terminal of the first capacitor and the output node and a fourth switch coupled to the first terminal of the first capacitor;
• and
• a controller coupled to the switching circuitry and configured to control a state of the switches, wherein, in at least one of the states, the first capacitor is connected between the input and output nodes by the switching circuitry.

A switched capacitor array circuit coupled to an input node and a output node, said array circuit comprising:

• a first capacitor having first and second terminals;
• switching circuitry coupled to the capacitors, said switching circuitry including,
• a first switch coupled intermediate the input node and the second terminal of the first capacitor;
• a second switch coupled intermediate the output node and the first terminal of the first capacitor;
• a first switch position located intermediate the second terminal of the first capacitor and a third node, a second switch position located intermediate the second terminal of the first capacitor and the output node, a third switch position located intermediate the first terminal of the first capacitor and the input node, a fourth switch position located intermediate the first terminal of the first capacitor and the third node and a fifth switch position located intermediate the first terminal of the first capacitor and a fourth node, with at least two of the switch positions containing a switch;
• and
• a controller coupled to the switching circuitry and configured to control a state of the switches, where, in at least one of the states, the first capacitor is connected between the input and the output nodes by the switching circuitry.