US 6,198,342 B1Granted

Charge pump circuit simple in construction and free from trouble even at low voltage

AssigneeSharp Kabushiki Kaisha

InventorKen Kawai

Life of this patent

Estimating the term…

Loading patent…

Abstract

In a charge pump circuit, the issues of increase in loss due to the backgating effect, increase in cost, risks of latch-up and charge leak and the like, which would be involved in achieving voltage reduction, are resolved with a simple circuit structure. A pump cell 31 has nMOS transistors M1-M3 and capacitors C1, C2. An auxiliary capacitor C is connected to an input node IN, and further p-well portions of the nMOS transistors M1-M3 are connected to this auxiliary capacitor C, the nMOS transistor M3 is interposed between each p-well portion and output node OUT, and the input node IN is connected to the gate of the nMOS transistor M3. Thus, with a simple circuit structure which involves only the use of the auxiliary capacitor C, voltage difference of the push-down of the p-well voltage is increased so that the deterioration of pump efficiency due to the backgating effect in the voltage reduction of power supply voltage is eliminated and that latch-up and charge leak are prevented.

Claims10

Dependent claims

A charge pump circuit having a plurality of pump cells connected in series, wherein a pump cell of an odd-numbered stage executes a charge pump operation for an input voltage based on a first clock signal and a second clock signal while a pump cell of an even-numbered stage executes a charge pump operation based on a third clock signal and a fourth clock signal so that an output voltage resulting from boosting the input voltage is obtained,

the pump cell being characterized in that:
drain of a first transistor and gate of a second transistor are connected to an input node;
source of the first transistor, source of the second transistor and one electrode of a first capacitor are connected to an output node;
drain of the second transistor and one electrode of a second capacitor are connected to a node connected to gate of the first transistor;
a clock input node to which one of the clock signals, whichever it is, is inputted is connected to the other electrodes of the first capacitor and the second capacitor;
one electrode of a third capacitor is connected to the input node;
a well portion of each transistor is connected to the other electrode of the third capacitor;
and that
the pump cell is equipped with switching means for electrically connecting or cutting off the well portion and the output node to or from each other.

6 more elements

Dependencies are inferred from the claim text.