US 6,195,032 B1 · Two-stage pipelined recycling analog-to-digital converter (ADC)

Abstract

An Analog-to-Digital Converter (ADC) contains two pipeline stages that operate in parallel on two different analog samples. Each pipeline stage includes two sub-stages. Each sub-stage has a low-resolution ADC element and a low-resolution DAC element. The ADC element converts the analog voltage input to the sub-stage into B digital bits, where B is a low number such as 1, 1.5, or 2. These digital bits are re-converted back to an analog DAC voltage by the DAC element. A subtractor then subtracts the analog DAC voltage from the sub-stage's analog input voltage to produce a difference voltage that represents the quantization error of the ADC/DAC elements. A multiplying amplifier multiplies the difference voltage by 2B to generate an output voltage to the next sub-stage. Each high-level pipeline stage acts as a recycling ADC, having a feedback switch that connects the output of the last sub-stage to the analog input of the first sub-stage. During successive clock periods, the first sub-stage converts B digital bits during a PH1 phase while the last sub-stage converts another B digital bits of less significance during the PH2 phase. The analog output from the last sub-stage is recycled back to the first sub-stage for the next clock and another 2B bits are converted in the next clock period. Once all of the MSB's have been converted, the last sub-stage outputs an analog residue voltage to the first sub-stage of the second pipeline stage, which then converts the LSB bits over several clock cycles using the same recycling method.

Claims20

Dependent claims

A pipelined recycling Analog-to-Digital Converter (ADC) comprising:

an analog sample input receiving an analog sample voltage;
a first pipeline stage, receiving the analog sample voltage, having:
an initial converter;
a final converter;
and
a feedback loop that connects an output voltage of the final converter to an input of the initial converter during recycling clock periods,
the first pipeline stage generating more-significant digital bits representing the analog sample voltage and outputting a residue voltage after several of the recycling clock periods;
a second pipeline stage, receiving the residue voltage from the first pipeline stage, having:
an initial converter;
a final converter;
and
a feedback loop that connects an output voltage of the final converter to an input of the initial converter during the recycling clock periods,
the second pipeline stage generating lower-significance digital bits representing the analog sample voltage over several of the recycling clock periods;
wherein the initial and final converter each comprise:
an analog input receiving an analog voltage;
an ADC element for converting the analog voltage to digital bits;
a digital-to-analog converter (DAC) element, coupled to the ADC element, for converting the digital bits to an analog DAC voltage;
a subtractor, receiving the analog voltage from the analog input and receiving the analog DAC voltage, for generating a difference voltage;
and
a multiplying amplifier for increasing a scale of the difference voltage to generate an output voltage;
whereby the feedback loops in each pipeline stage recycle analog voltages through the initial and final converters over several recycling clock periods.

18 more elements

A nested-pipeline Analog-to-Digital Converter (ADC) comprising:

a first recycling stage for converting an analog input voltage to most-significant bits (MSBs), the first recycling stage generating a final residue voltage representing a difference between the analog input voltage and a voltage represented by the MSBs;
a second recycling stage for converting the final residue voltage from the first recycling stage to least-significant bits (LSBs);
the first recycling stage having:
an initial sub-stage, having an analog input, for generating B digital bits of the MSB, the initial sub-stage having an ADC element and a DAC element, the ADC element converting the analog input to the B digital bits, the DAC element re-converting the B digital bits to a DAC voltage, the initial sub-stage outputting an intermediate voltage;
a final sub-stage, receiving the intermediate voltage from the initial sub-stage, for generating B digital bits of the MSB of less significance that the B digital bits generated by the initial sub-stage, the final sub-stage having an ADC element and a DAC element, the ADC element converting the intermediate voltage to the B digital bits, the DAC element re-converting the B digital bits to a DAC voltage, the final sub-stage outputting a final voltage;
a feedback switch for coupling the final voltage from the final sub-stage to the analog input voltage of the initial sub-stage during recycling clock periods;
a sampling switch, for connecting the analog input voltage to the analog input of the initial sub-stage during sampling clock periods;
the second recycling stage having:
an initial sub-stage, having an analog input, for generating C digital bits of the LSB, the initial sub-stage having an ADC element and a DAC element, the ADC element converting the analog input to the C digital bits, the DAC element re-converting the C digital bits to a DAC voltage, the initial sub-stage outputting an intermediate voltage;
a final sub-stage, receiving the intermediate voltage from the initial sub-stage, for generating C digital bits of the LSB of less significance that the C digital bits generated by the initial sub-stage, the final sub-stage having an ADC element and a DAC element, the ADC element converting the intermediate voltage to the C digital bits, the DAC element re-converting the C digital bits to a DAC voltage, the final sub-stage outputting a final voltage;
a second feedback switch for coupling the final voltage from the final sub-stage to the analog input voltage of the initial sub-stage during the recycling clock periods;
and
a second sampling switch, for connecting the analog input voltage to the analog input of the initial sub-stage during the sampling clock periods,
whereby the first and second recycling stages, each containing sub-stages, is an ADC with a nested pipeline structure.

11 more elements

A parallel-recycling Analog-to-Digital Converter (ADC) comprising:

sampling means, receiving an analog sample, for periodically sampling the analog sample to generate an analog-sample input voltage;
first recycling means, receiving the analog-sample input voltage during a sample period of a clock, for recycling analog voltages and generating digital bits representing lower-significance residues of the analog sample over a plurality of recycling periods of the clock that are not the sample period, the first recycling means outputting a final residue voltage at a next sample period after the plurality of recycling periods;
second recycling means, receiving the final residue voltage during the sample period of the clock, for recycling analog voltages and generating digital bits representing lower-significance residues of the analog sample over a plurality of recycling periods of the clock,
wherein the digital bits generated by the first recycling means represent most-significant-bits (MSBs) of the analog-sample input voltage, while digital bits generated by the second recycling means represent least-significant-bits (LSBs) of the analog-sample input voltage processed by the first recycling means during a previous plurality of the recycling periods of the clock,
whereby the first and second recycling means are pipelined.

2 more elements

Dependencies are inferred from the claim text.

Two-stage pipelined recycling analog-to-digital converter (ADC)

Life of this patent

Two-stage pipelined recycling analog-to-digital converter (ADC)

Life of this patent

Abstract

Claims20