Vertical transistor having top and bottom surface isolation
AssigneeTexas Instruments Incorporated
InventorSatwinder Malhi
Life of this patent
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Abstract
A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.
Claims3
A vertical transistor, comprising:
- a semiconductor substrate having top and bottom surfaces;
- a noncontinuous isolation layer in the semiconductor substrate between the top surface and the bottom surface;
- a source region formed in the top surface of the semiconductor substrate above the noncontinuous isolation layer;
- a gate electrode formed above the source region;
- a first insulating material extending from the top surface of the semiconductor substrate to the noncontinuous isolation layer;
- a drain region formed in the semiconductor substrate, a portion of the noncontinuous isolation layer extending into the drain region;
- and
- a second insulating material extending from the bottom surface of the semiconductor substrate to the noncontinuous isolation layer;
- wherein the noncontinuous isolation layer comprises oxide;
- wherein the first insulating material extending from the top surface of the semiconductor substrate to the noncontinuous isolation oxide layer comprises oxide;
- and
- wherein the second insulating material extending from the bottom surface of the semiconductor substrate to the noncontinuous isolation layer comprises polymide.
A plurality of adjacent vertical transistors, each of said plurality of vertical transistors comprising:
- a semiconductor substrate having top and bottom surfaces;
- a noncontinuous isolation layer in the semiconductor substrate between the top surface and the bottom surface;
- a source region formed in the top surface of the semiconductor substrate above the noncontinuous isolation layer;
- a gate electrode formed above the source region;
- a first insulating material extending from the top surface of the semiconductor substrate to the noncontinuous isolation layer;
- a drain region formed in the semiconductor substrate, a portion of the noncontinuous isolation layer extending into the drain region;
- and
- a second insulating material extending from the bottom surface of the semiconductor substrate to the noncontinuous isolation layer.
Dependencies are inferred from the claim text.