System for verifying signal timing accuracy on a digital testing device

In a testing device for testing integrated circuits having a plurality of test connectors disposed at a test head, each test connector having electrical conductors carrying electrical signals for a test channel, wherein each test channel corresponds to a circuit board that includes at least one driver and one receiver, a method for diagnosing component timing variances comprising the steps of:

• establishing an electrical connection between electrical conductors of a first and second test connector such that a first driver from a first circuit board is electrically connected across a low impedance path to a first receiver on a second circuit board;
• controlling the output of the first driver to drive an edge of an electrical signal at a predetermined time;
• detecting the signal received at the first receiver;
• and
• determining that the signal received at the first receiver is within a predetermined time period of the predetermined signal level output from the first driver.

In a testing device for testing integrated circuits having a plurality of test connectors disposed at a test head, each test connector having electrical conductors carrying electrical signals for a test channel, wherein each test channel corresponds to a circuit board that includes at least one driver and one receiver, a method for diagnosing component variances comprising the steps of:

• establishing an electrical connection between electrical conductors of a first and second test connector such that at a first driver from a first circuit board is electrically connected across a low impedance path to a first receiver on a second circuit board;
• delivering a control signal to the first driver to drive an output signal at a predetermined time;
• detecting the signal received at the first receiver;
• and
• verifying that the signal received at the first receiver is received within a predetermined time of the signal output from the first driver.

A computer readable storage medium containing program code for controlling the operation of a self test for an automatic testing device, comprising:

• a first code segment that contains program code that controls the output of a first driver on a first circuit board to drive an electrical signal at a predetermined time;
• a second code segment that contains program code that evaluates the signal timing received at a first receiver disposed on a second circuit board, that is configured to receive the signal output by the first driver;
• and
• a third code segment that contains program code that verifies that the signal timing received at the first receiver is within a predetermined tolerance of an allowable error of the driver and receiver of the first driver and first receiver.

In a testing device for testing integrated circuits having a plurality of test connectors disposed at a test head, each test connector having electrical conductors carrying electrical signals for a test channel, wherein each test channel corresponds to a circuit board that includes at least one driver and one receiver, a method for diagnosing component variances comprising the steps of:

• disposing a first test connector in an open, no-load configuration to obtain maximum impedance mismatch from a characteristic line impedance and thus obtain maximum signal reflection;
• controlling a first driver to drive an output signal at a predetermined time;
• detecting a reflected signal at a first receiver, the first receiver being disposed on the same circuit board as the first driver;
• and
• verifying that the signal received at the first receiver is received within a predetermined time of the signal output from the first driver.

An apparatus for testing component tolerance of a device for testing integrated circuits, the device having a plurality of test connectors disposed at a test head, each test connector having electrical conductors carrying electrical signals for a test channel, wherein each test channel corresponds to a circuit board that includes at least one driver and one receiver, the system comprising:

• a controller configured to control a first driver on a first circuit board to output an electrical signal at a predetermined time;
• evaluating means designed to detect a reflection of the electrical signal received at a first receiver on the first circuit board, wherein the test connector corresponding to the first circuit board is disposed in a no-load configuration so that maximum signal reflection is achieved;
• timing means configured to time a signal delay from the time that the first driver outputs an electrical signal to the time that the evaluating means detects the received signal;
• and
• verifying means responsive to the timing means for verifying that the reflected signal is received within an predetermined time.