US 6,192,489 B1 · Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation

Abstract

A mechanism for handling processing errors in a computer system. The mechanism includes a first means for processing a stream of instructions, second means for detecting an error caused by a timing dependant defect and occurring during processing of the instruction by the first means and third means for varying the instruction processing cycle time of the first means in response to the detection of the error by the second means, and for causing the second means to retry at least a portion of the instruction subsequent to the varying. In a preferred embodiment, the mechanism uses the variable frequency oscillator, controlled by recovery code, to increase the system clock cycle time by a specified time (Textend) following what has been determined to be a critical fail and after normal retry has been unsuccessful. The increased cycle time extends the net slack and, thereby, provides tolerance to certain AC (path delay) defects which have developed in any cycle time dependant latch to latch segment. The time (T) is chosen based on maximum cycle time restrictions resulting, for example, from the pipelining of data in system cables.

Claims2

Dependent claims

A computer system having a mechanism for handling processing errors, comprising:

first means for detecting an error occurring during processing of an instruction by said computer system;
second means, coupled to said first means, for causing said computer system to retry at least one operation subsumed by said instruction, in response to detection of said error;
third means, coupled to said second means, for determining whether said retry was successful;
fourth means, coupled to said second means and said third means and responsive to an indication by said third means that said retry was not successful, for varying an instruction processing cycle time of said computer system and for causing said second means to again retry said at least one operation subsequent to said varying;
and
fifth means, coupled to said fourth means, for initiating a deferred service call over a communications link in response to said varying, said deferred service call indicating that a digital computer system is operating in a degraded performance mode.

3 more elements

Dependencies are inferred from the claim text.

Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation

Life of this patent

Fault tolerant design for identification of AC defects including variance of cycle time to maintain system operation

Life of this patent

Abstract

Claims2