Apparatus and method for detecting microbranches early

A microprocessor comprising:

• an instruction cache;
• a microcode instruction unit coupled to said instruction cache, said microcode instruction unit including:
• a storage device including a plurality of lines for storing a plurality of microcode instructions and a plurality of control fields, wherein said plurality of control fields are associated with said plurality of microcode instructions, and wherein said storage device is configured to output at least a first microcode instruction of said plurality of microcode instructions and a first control field of said plurality of control fields in response to a first address;
• and
• a sequence control unit coupled to receive said first control field from said storage device, wherein said first control field corresponds to a subsequent microcode instruction in a microcode sequence with said first microcode instruction, and wherein said first control field further includes an indication indicative of whether or not said subsequent microcode instruction is a last microcode instruction in said microcode sequence, and wherein said sequence control unit is configured to assert a signal responsive to said indication indicating that said subsequent microcode instruction is said last microcode instruction.

A computer system comprising:

• a microprocessor comprising:
• an instruction cache;
• a microcode instruction unit coupled to said instruction cache, said microcode instruction unit including:
• a storage device including a plurality of lines for storing a plurality of microcode instructions and a plurality of control fields, wherein said plurality of control fields are associated with said plurality of microcode instructions, and wherein said storage device is configured to output at least a first microcode instruction of said plurality of microcode instructions and a first control field of said plurality of control fields in response to a first address;
• and
• a sequence control unit coupled to receive said first control field from said storage device, wherein said first control field corresponds to a subsequent microcode instruction in a microcode sequence with said first microcode instruction, and wherein said first control field further includes an indication indicative of whether or not said subsequent microcode instruction is a last microcode instruction in said microcode sequence, and wherein said sequence control unit is configured to assert a signal responsive to said indication indicating that said subsequent microcode instruction is said last microcode instruction;
• and
• an input/output (I/O) device coupled to said microprocessor, wherein said I/O device is configured to communicate between said computer system and another computer system to which said I/O device is coupled.