Executing partial-width packed data instructions

A method of performing packed data operations comprising the steps of:

• receiving a single macro instruction specifying at least two logical registers in a packed data register file, wherein the two logical registers respectively store a first packed data operand and second packed data operand having a first and second plurality of corresponding data elements;
• and
• independently operating on the first and second plurality of corresponding data elements from the first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements by,
• performing an operation specified by the single macro instruction on at least one pair of corresponding data elements in the first and second plurality of corresponding data elements to produce at least one resulting data element in each of the first and second plurality of resulting data elements, and
• setting remaining resulting data elements in the first and second plurality of resulting data elements to one or more predetermined values;
• and
• storing the first and second plurality of resulting data elements in a single logical register as a third packed data operand.

A method of performing packed data operations comprising:

• receiving a macro instruction specifying one or more logical source registers containing a first packed data operand and a second packed data operand;
• converting the macro instruction into a first and second set of packed data micro instructions;
• dividing the first and second packed data operands each into a first and second set of one or more corresponding data elements;
• responsive to execution of the first set of packed data micro instructions, causing the operation specified by the macro instruction to be performed on at least one pair of corresponding data elements from the first set of one or more corresponding data elements to produce a resulting one or more data elements;
• responsive to execution of the second set of packed data micro instructions, causing the operation specified by the macro instruction to be independently performed on at least one pair of corresponding data elements from the second set of one or more corresponding data elements to produce a second resulting one or more data elements.

A processor comprising:

• a decoder to receive a macro instruction specifying one or more logical source registers containing a first packed data operand and a second packed data operand;
• the decoder to convert the macro instruction into a first and second set of packed data micro instructions;
• the first and second packed data operands each having a first and second set of one or more corresponding data elements;
• an execution unit to execute the first set of packed data micro instructions, causing the operation specified by the macro instruction to be performed on at least one pair of corresponding data elements from the first set of one or more corresponding data elements to produce a resulting one or more data elements;
• and
• when instructed to do so, the execution unit to set one or more data elements to a predetermined value.

A machine-readable medium having stored thereon data representing sequences of instructions, the sequences of instructions which, when executed by a processor, cause the processor to perform operations comprising:

• receiving a single macro instruction specifying at least two logical registers in a packed data register file, wherein the two logical registers respectively store a first packed data operand and a second packed data operand having a first and second plurality of corresponding data elements;
• and
• independently operating on the first and second plurality of corresponding data elements from the first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements by,
• performing an operation specified by the single macro instruction on at least one pair of corresponding data elements in the first and second plurality of corresponding data elements to produce at least one resulting data element in each of the first and second plurality of resulting data elements, and
• setting remaining resulting data elements in the first and second plurality of resulting data elements to one or more predetermined values;
• and
• storing the first and second plurality of resulting data elements in a single logical register as a third packed data operand.

A machine readable medium having instructions stored thereon which, when executed by a machine, cause the machine to perform operations comprising:

• receiving a macro instruction specifying one or more logical source registers containing a first packed data operand and a second packed data operand;
• converting the macro instruction into a first and second set of packed data micro instructions;
• dividing the first and second packed data operands each into a first and second set of one or more corresponding data elements;
• responsive to executing the first set of packed data micro instructions, causing the operation specified by the macro instruction to be performed on at least one pair of corresponding data elements from the first set of one or more corresponding data elements to produce a resulting one or more data elements;
• and
• responsive to executing the second set of packed data micro instructions, causing the operation specified by the macro instruction to be independently performed on at least one pair of corresponding data elements from the second set of one or more corresponding data elements to produce a second resulting one or more data elements.