Method and apparatus for decoding one or more instructions after renaming destination registers
AssigneeIntel Corporation
InventorMillind Mittal
Life of this patent
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Abstract
In one aspect the present invention provides for a method for executing a sequence of instructions in a processor. The method comprises decoding a first the instructions into one or more first micro-ops, renaming destination registers identified in a first portion of the first micro-ops by reassigning available additional physical registers for the destination registers, and decoding a second portion of the first micro-ops into one or more second micro-ops. The act of renaming has renamed a destination register of at least one micro-op of the second portion of the first micro-ops. The method executes a third portion of the first and the second micro-ops.
Claims36
A method comprising:
- renaming at least one destination register for one or more micro-ops of a first set of one or more micro-ops;
- decoding one or more micro-ops of the first set into a second set of one or more micro-ops, wherein the decoding comprises decoding at least one micro-op having a renamed destination register;
- and
- executing one or more micro-ops from the first set and/or one or more micro-ops from the second set.
An apparatus comprising:
- a renamer to rename destination registers for a first set of instructions having a first subset of instructions and a second subset of instructions;
- at least one expander to decode the first subset of instructions into a second set of instructions, wherein the at least one expander decodes an instruction of the first subset after any destination registers for that instruction have been renamed by the renamer;
- and
- at least one execution unit to execute the second subset of instructions and the second set of instructions.
A processor comprising:
- at least one decoder for decoding a first set of instructions into a second set of instructions having a first subset of instructions and a second subset of instructions;
- a renamer to rename destination registers for the second set of instructions;
- at least one expander to decode the first subset of instructions into a third set of instructions, wherein the at least one expander decodes an instruction of the first subset after any destination registers for that instruction have been renamed by the renamer;
- a scheduler for scheduling an order of execution for the second subset of instructions and the third set of instructions;
- and
- at least one execution unit to execute the second subset of instructions and the third set of instructions.
An apparatus comprising:
- means for decoding a first set of instructions into a second set of instructions having a first subset of instructions and a second subset of instructions;
- means for renaming destination registers for the second set of instructions;
- means for decoding the first subset of instructions into a third set of instructions such that each instruction of the first subset is decoded after any destination registers for that instruction have been renamed;
- means for ordering execution of the second subset of instructions and the third set of instructions;
- and
- means for executing the second subset of instructions and the third set of instructions.
An apparatus comprising:
- means for renaming destination registers for a first set of instructions having a first subset of instructions and a second subset of instructions;
- means for decoding the first subset of instructions into a second set of instructions such that each instruction of the first subset is decoded after any destination registers for that instruction have been renamed;
- and
- means for executing the second subset of instructions and the second set of instructions.
Dependencies are inferred from the claim text.