Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor
AssigneeMicrochip Technology Incorporated
InventorsSumit K. Mitra, Joseph W. Triece
Life of this patent
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Abstract
A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
Claims21
A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in said processor architecture scheme comprising the steps of:
- providing an instruction set for said processor to execute;
- dedicating a first section of each instruction of said instruction set to identify where each instruction is to be executed;
- establishing an indirect addressing pointer in memory;
- and
- establishing a dedicated set of said virtual register addresses in said memory equal to a number of indirect addressing modes associated with said indirect addressing pointer wherein each of said virtual register address locations dictate an indirect addressing mode to be used with said indirect addressing pointer when accessed thereby allowing flexibility of selecting addressing modes dynamically on an instruction by instruction basis.
A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in said processor architecture scheme comprising, in combination:
- a central processing unit for executing said instruction;
- a memory coupled to said CPU for storing data;
- a pointer register in said memory for storing an address location where said instruction is to access when an address associated with said pointer register is accessed;
- dedicated virtual register address locations in said memory associated with said pointer register which dictates an indirect addressing mode to be used with said pointer register when one of said dedicated address locations is accessed thereby allowing flexibility of selecting addressing modes dynamically on an instruction by instruction basis.
Dependencies are inferred from the claim text.