Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache

A superscalar microprocessor comprising:

• a stack cache configured to store data bytes associated with stack-relative memory accesses;
• a data cache configured to store data bytes associated with memory accesses;
• a reorder buffer including:
• a request bus configured to convey an access address;
• a plurality of storage locations wherein each of said plurality of storage locations is configured to store information pertaining to an instruction including an address of an operand;
• a plurality of comparator circuits wherein each of said plurality of comparator circuits is coupled to a respective one of said plurality of storage locations to receive said address, and wherein said each of said plurality of comparator circuits is coupled to said request bus, and wherein each of said plurality of comparator circuits is configured to produce a comparison signal indicative of equality between a field of said address and a corresponding field of said access address;
• and
• a control unit coupled to said plurality of storage locations and to said request bus, and further coupled to each of said plurality of comparator circuits to receive said comparison signal, wherein said control unit is configured to convey a dependency signal indicative of a dependency between said access address and said address according to said comparison signals, and wherein said control unit is configured to convey said dependency signal upon a dependency bus;
• a plurality of decode units configured to decode instructions wherein said plurality of decode units are coupled to said dependency bus;
• and
• a load/store unit configured to execute read and write memory accesses wherein said load/store unit is coupled to said request bus, to said dependency bus, to said data cache, and to said stack cache.