Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle

A method for processing store instructions in a processor, the method comprising the steps of:

• (a) dispatching a first store instruction and at least one additional store instruction from a dispatch unit;
• (b) executing the first store instruction to determine a real address memory location for storing data targeted by the first store instruction, and to determine an entry in a register file containing the data targeted by the first store instruction, the register file comprising alternatively an architected register file and rename register file;
• (c) passing the data targeted by the first store instruction from the entry in the register file to an entry in a data queue before the first store instruction completes, said data targeted by the first store instruction passing through a multiplexer arrangement between the data queue and the architected register file and rename register file;
• (d) executing at least one additional store instruction to determine a real address memory location for storing data targeted by the respective additional store instruction and to determine an entry in the register file containing data targeted by the respective additional store instruction;
• (e) passing the data targeted by the respective additional store instruction from the register file to a respective additional entry in the data queue before the respective additional store instruction completes, said data targeted by the respective additional store instruction passing through the multiplexer between the data queue and architected register file and rename register file;
• (f) passing the data targeted by the first store instruction and the data targeted by at least one of the additional store instructions from the data queue to cache memory upon completion of the first store instruction and said at least one additional store instruction in a single clock cycle.