High performance cache directory addressing scheme for variable cache sizes utilizing associativity
AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
Life of this patent
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Abstract
To avoid multiplexing within the critical address paths, the same address field is employed as a index to the cache directory and cache memory regardless of the cache memory size. An increase in cache memory size is supported by increasing associativity within the cache directory and memory, for example by increasing congruence classes from two members to four members. For the smaller cache size, an additional address “index” bit is employed to select one of multiple groups of address tags/data items within a cache directory or cache memory row by comparison to a bit forced to a logic 1.
Claims22
A method of addressing a cache directory for a variable size cache, comprising:
- selecting at least one congruence class within a cache directory utilizing an index field from an address;
- for a first cache size, employing an address bit from the address to either
- select a congruence class among congruence classes selected utilizing the index field, or
- select one group of cache directory entries within a congruence class selected utilizing the index field;
- for a second cache size, comparing a mode bit to a predetermined logic state at one or more comparators comparing an address tar to cache directory entries to enable selection of any cache directory entry within the selected congruence class or group of cache directory entries;
- comparing an address tag field from the address to each cache directory entry within the selected congruence class or group of cache directory entries;
- and
- responsive to identifying a match between a cache directory entry and the address tag field, selecting a portion of a cache memory associated with the matching cache directory entry.
A cache directory addressing mechanism for a variable size cache, comprising:
- a cache directory containing a plurality of congruence classes, each congruence class including n groups of m cache directory entries;
- a cache memory containing a plurality of congruence classes, each congruence class including n groups of m cache lines, each group of cache lines in a congruence class associated with a corresponding group of cache directory entries in a same congruence class of the cache directory;
- selection logic selecting at least one congruence class within the cache directory utilizing an index field from an address, wherein the selection logic
- (a) for a first cache size, employs an address bit from the address either
- (1) as a late select within the cache directory or
- (2) to select group of cache directory entries within the selected congruence class, and
- (b) for a second cache size, compares a mode signal to a predetermined logic state at one or more comparators comparing an address tag to cache directory entries to enable selection of any cache directory within the selected congruence class or group of cache directory entries;
- at least one comparator comparing an address tag field from the address to each cache directory entry within the selected group of cache directory entries;
- and
- a multiplexer selecting a cache line in the cache memory corresponding to a matching cache directory entry in response to a match being identified between a cache directory entry within the selected group of cache directory entries and the address tag field.
A method of addressing a cache directory for a variable size cache, comprising:
- selecting a congruence class within a cache directory utilizing an index field from an address;
- for a first cache size, comparing an address tag field from the address to each cache directory entry within the selected group of cache directory entries;
- for a second cache size, comparing a portion of the address tag field and a mode bit to each cache directory entry;
- and
- responsive to identifying a match of either the address tag field for the first cache size or the portion of the address tag field and the mode bit for the second cache size to a cache directory entry, selecting a portion of a cache memory associated with the matching cache directory entry.
A method of addressing a cache directory for a variable size cache, comprising:
- selecting a congruence class within a cache directory utilizing an index field from an address;
- for a first cache size, employing an address bit from the address to select one group of cache directory entries within the selected congruence class;
- for a second cache size, selecting one group or cache directory entries within the selected congruence class;
- comparing an address tag field from the address to each selected cache directory entry;
- and
- responsive to identifying a match between a selected cache directory entry and the address tag field, selecting a portion of a cache memory corresponding to the matching cache directory entry.
Dependencies are inferred from the claim text.