Apparatus and method for optimizing performance of a cache memory in a data processing system
AssigneeMotorola, Inc.
InventorsJoseph C. Circello, Anup S. Tirumala, Vasudev J. Bibikar
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Abstract
A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15). If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
Claims14
A data processing system having a cache, comprising:
- a data memory;
- a fill buffer for storing a missed data value, wherein the fill buffer comprises a number of segments;
- and
- a control register having at least one bit for storing a first state and a second state, wherein the control register determines the number of segments of the fill buffer used to store the missed data value and wherein only a portion of the segments of the fill buffer are used to store the missed data value when the bit is in the second state.
A data processing system for generating a processor address and having a cache comprising:
- a data memory;
- a fill buffer having a plurality of segments for storing a missed data value, wherein the processor address refers to one of the plurality of segments;
- and
- a control register having a plurality of bits used in conjunction with the processor address to determine a number of the plurality of segments in the fill buffer to be filled with data for storing the missed data value, wherein when the plurality of bits are set in a first state, only a portion of the number of the plurality of segments is used to store the missed data.
A method for operating a cache in a data processing system, the cache having a fill buffer, wherein the fill buffer comprises a plurality of segments, a control register, and a data memory, and the method comprising the steps of:
- setting one or more bits in the control register indicating a condition for loading the fill buffer with a missed data value, wherein the one or more bits indicates how many of the plurality of segments are used to store the missed data value and wherein at least one state of the one or more bits indicates that only a portion of the plurality of segments are to be used to store the missed data value;
- generating a processor address that is coupled to the data processing system, wherein the processor address is not in the cache;
- loading the missed data value into the fill buffer;
- and
- wherein the condition used to store the missed data value in the fill buffer is further determined by the processor address.
Dependencies are inferred from the claim text.