Method and apparatus for resetting a random access memory
AssigneeCompaq Computer Corporation
InventorMark A. Shand
Life of this patent
Estimating the term…
Abstract
A resettable memory apparatus includes a random access memory including a plurality of memory locations, each memory location stores a plurality of bits of data. A single register has a plurality of bits, there is one bit for each of the plurality of memory locations. A reset signal resets all of the bits in the register to invalid. A reset value is generated when reading a particular one of the memory locations while the corresponding bit in the register is invalid to provide a resettable random access memory. Writing data to the particular memory location sets the corresponding bit in the register to valid. Subsequent reads to the location while produced the data stored therein as long as the corresponding bit in the register remains valid.
Claims29
A resettable memory apparatus including a random access memory having a plurality of memory locations, each of the plurality of memory locations storing a plurality of bits of data, comprising:
- a register having a plurality of bits, there being one bit for each of the plurality of memory locations;
- means for resetting all of the bits in the register to invalid;
- an address recoder for recoding an address of any of the plurality of memory locations to a reset address when accessing the address in the random access memory while a bit of the plurality of bits in the register that corresponds to the address is invalid;
- a multiplexer having a first input connected to the output of the address recoder and a second input connected to a base address register, the multiplexer selecting by a park signal an input address for the random access memory and a base location of the random access memory storing a base address to read when the second input of the multiplexer is selected;
- and
- means for generating a reset value when reading a particular one of the memory locations while the corresponding bit in the register is invalid to provide a resettable random access memory.
A method for accessing a random access memory having a plurality of memory locations, each of the plurality of memory locations storing a plurality of bits of data, comprising:
- resetting a plurality of bits in a register to invalid in response to a reset signal, there being one bit for each of the plurality of memory locations;
- recoding to a reset address, in an address recoder, any address of the plurality of memory locations to which corresponds a bit of the plurality of bits in the register that is invalid when accessing the random access memory;
- selecting based on a park signal, by a multiplexer having a first input connected to an output of the address recoder and a second input connected to a base address register, an input address for the random access memory and a base location of the random access memory storing a base address to read when the second input of the multiplexer is selected;
- and
- generating a reset value when reading a particular one of the memory locations while the corresponding bit in the register is invalid to provide a resettable access memory.
A resettable memory device including a random access memory having memory locations, each of the memory locations storing bits of data, comprising:
- a register having bits, there being one bit in the register for each of the memory locations;
- means for resetting all of the bits in the register to invalid in response to a reset signal;
- an address recoder capable of recoding to a reset address a memory address of any one of the memory locations while its corresponding bit in the register is invalid, such that for a read access of the memory address the address recoder provides at its output the reset address while the corresponding bit is invalid and the memory address while the corresponding bit is valid;
- means for providing a known reset value as a data output in place of data from any one of the memory locations which is being read-accessed while the corresponding bit from among the bits of the register is invalid;
- and
- a multiplexer having an output connected to the random access memory, a first input connected to the output of the address recoder and a second input connected to a base address register, based on a park signal the multiplexer selecting between the first and second inputs, such that when the first input is selected either the reset address or the memory address are selected, and such that when the second input address is selected an address of the base address register is selected wherein a resettable random access memory is provided.
A method for accessing a random access memory having memory locations, each of the memory locations storing bits of data, comprising:
- resetting bits in a register to invalid in response to a reset signal, there being one bit in the register for each of the memory locations;
- providing a known reset value as a data output in place of data from any one of the memory locations which is being read-accessed while a corresponding bit from among the bits of the register is invalid, such that a resettable random access memory is provided;
- recoding in an address recoder a particular address to a reset address when accessing the random access memory while the corresponding bit from among the bits in the register is invalid;
- and
- selecting based on a park signal, by a multiplexer having a first input connected to an output of the address recoder and a second input connected to a base address register, an input address for the random access memory and a base location of the random access memory storing a base address to read when the second input of the multiplexer is selected.
Dependencies are inferred from the claim text.