Interrupt controller
AssigneeIntel Corporation
InventorsKenneth C. Haren, Tuan Quach
Life of this patent
Estimating the term…
Abstract
An interrupt controller includes conductors for receiving interrupt request signals, a memory, a register and control logic. Each of the interrupt request signals are capable of indicating an interrupt request. The memory is capable of storing information about the interrupt request signals, and the register is writable to identify a set of locations of the memory for scanning. The control logic scans the set of locations for interrupt requests and does not scan other locations of the memory for interrupt requests. In some cases, the number of interrupt request signals are exceeds the number of locations. For these cases, information about selected interrupt signals are stored in the locations.
Claims26
An interrupt controller comprising:
- conductors that receive interrupt request signals, each of the interrupt request signals being capable of indicating an interrupt request;
- a memory including locations capable of storing information about the interrupt request signals;
- a register writable to identify a first set of the locations for scanning and a second set of the locations;
- and
- control logic to scan the first set of locations for interrupt requests and not scan the second set of locations for interrupt requests.
A method comprising:
- receiving interrupt request signals, each of the interrupt request signals being capable of indicating an interrupt request;
- allocating memory locations to store information about the interrupt request signals;
- storing scanning information identifying a set of the memory locations to be scanned;
- and
- scanning the set of the memory locations to detect the interrupt requests and not scanning the remaining memory locations.
An interrupt controller comprising:
- conductors to receive indications of external interrupt requests;
- assertion logic to generate indications of internal interrupt requests;
- an interrupt request information memory including locations to store information about the internal interrupt requests and the external interrupt requests;
- register bits to provide logical indications to selectively mask out locations of the memory to not be scanned;
- and
- control logic to scan the locations in memory based upon the logical indications.
A method comprising:
- allocating memory locations to store interrupt information;
- receiving a first plurality of interrupt request signals;
- generating a second plurality of interrupt request signals;
- identifying a selection of the first and second plurality of interrupt request signals;
- storing interrupt information for the identified selection in the memory locations;
- and
- scanning the memory locations to retrieve interrupt information based on the identifying.
An interrupt controller comprising:
- conductors that receive interrupt request signals, each of the interrupt request signals being capable of indicating an interrupt request;
- a memory including contiguous locations capable of storing information about the interrupt request signals;
- a register writable to identify a first non-contiguous set of the locations for scanning and a second set of the locations;
- and
- control logic to scan the first set of locations for interrupt requests and not scan the second set of locations for interrupt requests.
A method comprising:
- receiving interrupt request signals, each of the interrupt request signals being capable of indicating an interrupt request;
- allocating contiguous memory locations to store information about the interrupt request signals;
- storing scanning information identifying a non-contiguous set of the memory locations to be scanned;
- and
- scanning the set of the memory locations to detect the interrupt requests and not scanning the remaining memory locations.
Dependencies are inferred from the claim text.