Apparatus for postponing processing of interrupts by a microprocessor

An interrupt control device for controlling an interrupt generated by an entity, said interrupt to be processed by a second device, the control device comprising:

• an interrupt register to receive an interrupt word representing an interrupt request from a respective entity;
• a memory size register including information regarding a size of a memory area associated with the respective entity;
• an address register including information regarding a first address of the respective memory area associated with the respective entity;
• and
• a logic circuit operatively coupled to the interrupt register, the memory size register and the address register to store the interrupt word received from the interrupt register at the first address in the memory area associated with the respective entity;
• wherein the storing of the interrupt word in the memory area does not cause an interrupt signal to initiate interrupt processing by the second device of interrupt words stored in the interrupt register.

An interrupt control device for controlling storage of an interrupt word representing an interrupt request generated by a respective entity and directed to a second device, the control device comprising:

• an input register to receive the interrupt word;
• and
• a logic circuit, operatively coupled to the input register, to calculate a memory address and to store the interrupt word in a memory at the calculated memory address,
• wherein the storing of the interrupt word in the memory does not cause an interrupt signal to initiate interrupt processing by the second device of interrupt words stored in the memory.

A system comprising:

• a microprocessor;
• an interrupt receiver register to receive an interrupt word representing an interrupt request generated by an entity and directed to a microprocessor;
• a memory operatively coupled to the microprocessor;
• and
• a logic circuit, operatively coupled to the interrupt receiver register and the memory, the logic circuit to calculate a memory address and to store the interrupt word at the calculated memory address in the memory;
• wherein the microprocessor is programmed to retrieve the interrupt word stored at the calculated memory address and also programmed to process the retrieved interrupt word, and
• wherein the microprocessor does not initiate its retrieving and processing of the interrupt word in response to the logic circuit causing an interrupt signal after storing interrupt words in the memory.

A method for controlling interrupts generated by a first entity associated with a microprocessor, the method comprising steps of:

• partitioning a memory to include a first memory area for the first entity;
• receiving a first interrupt word from the first entity, the first interrupt word representing a first interrupt request generated by the first entity and to be processed by the microprocessor;
• storing the first interrupt word in the first partitioned memory area at a first memory address without causing an interrupt signal to be sent to the microprocessor;
• the microprocessor retrieving the stored first interrupt word from the first partitioned memory area;
• and
• the microprocessor processing the first entity associated with the retrieved first interrupt word,
• wherein the microprocessor does not initiate its retrieving and processing of the first interrupt word in response to interrupt words being stored in the first partitioned memory.

A system for storing interrupts generated by an entity, the system comprising:

• an interrupt register to receive first and second interrupt words representing, respectively, first and second interrupt requests from the entity;
• a memory size register including information regarding a size of a memory area associated with the entity;
• an address register including information regarding a first address and a second address in the memory area associated with the entity;
• a logic circuit operatively coupled to the interrupt register, the memory size register and the address register to store the first and second interrupt words received from the interrupt register at, respectively, the first and second addresses in the memory area associated with the entity;
• a microprocessor;
• and
• a memory operatively coupled to the microprocessor and the logic circuit, the memory including the memory area associated with the entity,
• wherein the storing of the first and second interrupt words does not cause an interrupt signal to initiate interrupt processing by the microprocessor of the interrupt words stored in the memory.