PCI-compliant interrupt steering architecture
AssigneeHewlett-Packard Company
InventorsPaul Grunewald, Wesley H. Stelter, Jiangang Ding
Life of this patent
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Abstract
An interrupt steering architecture that enables an intelligent peripheral device to process interrupts from PCI devices associated with a PCI bus is disclosed. The interrupt steering architecture enables the PCI interrupt signals to be steered to either a host CPU or to an intelligent peripheral device. The interrupt steering architecture is wholly compliant with the PCI bus specification and does not utilize additional sideband signals. The interrupt steering architecture is under user control and can be set by the user at system initialization or reset.
Claims20
A computer system, comprising:
- a plurality of interrupt signals;
- a first and a second CPU in communication with the interrupt signals;
- a first interrupt steering device operatively coupled to the interrupt signals and to the first CPU, the first interrupt steering device having a capability to steer a first one of the interrupt signals to the first CPU;
- and
- a second interrupt steering device operatively coupled to the interrupt signals and to the second CPU, the second interrupt steering device having a capability to steer a second one of the interrupt signals to the second CPU while the first interrupt steering device steers the first one of the interrupt signals to the first CPU.
A method for operating a computer system, the computer system including a first CPU and a second CPU operatively coupled to a communication link including a plurality of interrupt signals, the method comprising the steps of:
- providing a first and second interrupt steering mechanism operatively coupled to the communication link, the second interrupt steering mechanism distinct from the first interrupt steering mechanism;
- enabling the second interrupt steering mechanism to steer a first select one of the interrupt signals to the second CPU;
- and
- disabling the first interrupt steering mechanism from steering the first select one of the interrupt signals to the first CPU;
- wherein the second interrupt steering mechanism has a capability to steer a second one of the interrupt signals to the second CPU while the first interrupt steering mechanism steers a first one of the interrupt signals to the first CPU.
A computer system, comprising:
- a first and second processing devices responsive to interrupts;
- a first and second interrupt controllers, the first interrupt controller generates interrupts to the first processing device, the second interrupt controller generates interrupts to the second processing device;
- a communication link including a plurality of interrupt signals;
- a first interrupt steering device operatively coupled to the communication link and to the first interrupt controller, the first interrupt steering device receiving the interrupt signals from the communication link and transmitting select ones of the interrupt signals to the first interrupt controller;
- a first interrupt assist device coupled to the first interrupt steering device, the first interrupt assist device indicating to the first interrupt steering device the select ones of the interrupt signals;
- a second interrupt steering device operatively coupled to the communication link and the second interrupt controller, the second interrupt steering device distinct from the first interrupt steering device, the second interrupt steering device receiving the interrupt signals from the communication link and transmitting designated ones of the interrupt signals to the second interrupt controller;
- and
- a second interrupt assist device, the second interrupt assist device indicating to the second interrupt steering device the designated ones of the interrupt signals;
- wherein the second interrupt steering device has a capability to steer a second one of the interrupt signals to the second processing device while the first interrupt steering device steers a first one of the interrupt signals to the first processing device.
Dependencies are inferred from the claim text.