Method/apparatus for dynamically changing FIFO draining priority through asynchronous or isochronous DMA engines in response to packet type and predetermined high watermark being reached

An apparatus comprising:

• a first-in/first-out (FIFO) to receive data from one or mote devices from a first bus;
• a data count circuit coupled to the FIFO to determine a difference, the difference being a difference between a location where a receiving unit of data is to be written and a location where a draining unit of data is to be drained in the FIFO;
• a comparator to compare the difference with a predetermined high watermark value;
• a priority generation circuit coupled to the comparator, the priority generation circuit to provide a priority drain signal in response to the difference being equal to or alternatively greater than the predetermined high watermark value;
• and
• a direct memory access (DMA) circuit coupled to the priority generation circuit and the data count circuit, the DMA circuit to assert a signal to a bus arbiter to access a second bus having a plurality of devices coupled thereto, responsive to the difference being greater than the predetermined high watermark value, the DMA circuit to assert a priority signal to the bus arbiter to access the second bus over other pending signals received by the bus arbiter from other devices.

A system, comprising:

• a first bus having a first plurality of devices coupled thereto and a second bus having a second plurality of devices coupled thereto;
• and
• a module coupled between the first and second buses for temporarily storing data received from one or more of the first plurality of devices on the first bus and for draining the data to one or more of the second plurality of devices on the second bus, the module comprising:
• a first-in/first-out (FIFO) to receive data;
• a data count circuit coupled to the FIFO to determine a difference, the difference being a difference between a location where a receiving unit of data is to be written and a location where a draining unit of data is to be drained,
• a comparator to compare the difference with a predetermined high watermark value,
• a priority generation circuit coupled to the comparator, the priority generation circuit to provide a priority drain signal in response to the difference being equal to or alternatively greater than the predetermined high watermark value, and
• a direct memory access (DMA) circuit coupled to the priority generation circuit and the data count circuit, the DMA circuit to assert a signal to a bus arbiter to access a second bus having a plurality of devices coupled thereto, responsive to the difference being greater than the predetermined high watermark value, the DMA circuit to assert a priority signal to the bus arbiter to access the second bus over other pending signals received by the bus arbiter from other devices.